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Warning, cross-references for /kernel/drivers/net/bnx2.h need to be fixed.

0001 /*                    The Quest Operating System
0002  *  Copyright (C) 2005-2010  Richard West, Boston University
0003  *
0004  *  This program is free software: you can redistribute it and/or modify
0005  *  it under the terms of the GNU General Public License as published by
0006  *  the Free Software Foundation, either version 3 of the License, or
0007  *  (at your option) any later version.
0008  *
0009  *  This program is distributed in the hope that it will be useful,
0010  *  but WITHOUT ANY WARRANTY; without even the implied warranty of
0011  *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
0012  *  GNU General Public License for more details.
0013  *
0014  *  You should have received a copy of the GNU General Public License
0015  *  along with this program.  If not, see <http://www.gnu.org/licenses/>.
0016  */
0017 
0018 /* Broadcom NetXtreme II driver */
0019 
0020 #ifndef _NET_BNX2_H_
0021 #define _NET_BNX2_H_
0022 #include "types.h"
0023 #include "smp/spinlock.h"
0024 #include "drivers/net/skbuff.h"
0025 
0026 #define PAGE_SHIFT 12
0027 #define PORT_TP    0x00
0028 #define PORT_FIBRE 0x03
0029 
0030 #define FLOW_CTRL_TX 0x01
0031 #define FLOW_CTRL_RX 0x02
0032 
0033 #define PCI_VENDOR_ID_BROADCOM      0x14e4
0034 #define PCI_VENDOR_ID_HP        0x103c
0035 #define PCI_VENDOR_ID_AMD       0x1022
0036 #define PCI_DEVICE_ID_AMD_8132_BRIDGE   0x7458
0037 #define PCI_DEVICE_ID_TIGON3_5752   0x1600
0038 #define PCI_DEVICE_ID_TIGON3_5752M  0x1601
0039 #define PCI_DEVICE_ID_NX2_5709      0x1639
0040 #define PCI_DEVICE_ID_NX2_5709S     0x163a
0041 #define PCI_DEVICE_ID_TIGON3_5700   0x1644
0042 #define PCI_DEVICE_ID_TIGON3_5701   0x1645
0043 #define PCI_DEVICE_ID_TIGON3_5702   0x1646
0044 #define PCI_DEVICE_ID_TIGON3_5703   0x1647
0045 #define PCI_DEVICE_ID_TIGON3_5704   0x1648
0046 #define PCI_DEVICE_ID_TIGON3_5704S_2    0x1649
0047 #define PCI_DEVICE_ID_NX2_5706      0x164a
0048 #define PCI_DEVICE_ID_NX2_5708      0x164c
0049 #define PCI_DEVICE_ID_TIGON3_5702FE 0x164d
0050 #define PCI_DEVICE_ID_NX2_57710     0x164e
0051 #define PCI_DEVICE_ID_NX2_57711     0x164f
0052 #define PCI_DEVICE_ID_NX2_57711E    0x1650
0053 #define PCI_DEVICE_ID_TIGON3_5705   0x1653
0054 #define PCI_DEVICE_ID_TIGON3_5705_2 0x1654
0055 #define PCI_DEVICE_ID_TIGON3_5721   0x1659
0056 #define PCI_DEVICE_ID_TIGON3_5722   0x165a
0057 #define PCI_DEVICE_ID_TIGON3_5723   0x165b
0058 #define PCI_DEVICE_ID_TIGON3_5705M  0x165d
0059 #define PCI_DEVICE_ID_TIGON3_5705M_2    0x165e
0060 #define PCI_DEVICE_ID_TIGON3_5714   0x1668
0061 #define PCI_DEVICE_ID_TIGON3_5714S  0x1669
0062 #define PCI_DEVICE_ID_TIGON3_5780   0x166a
0063 #define PCI_DEVICE_ID_TIGON3_5780S  0x166b
0064 #define PCI_DEVICE_ID_TIGON3_5705F  0x166e
0065 #define PCI_DEVICE_ID_TIGON3_5754M  0x1672
0066 #define PCI_DEVICE_ID_TIGON3_5755M  0x1673
0067 #define PCI_DEVICE_ID_TIGON3_5756   0x1674
0068 #define PCI_DEVICE_ID_TIGON3_5751   0x1677
0069 #define PCI_DEVICE_ID_TIGON3_5715   0x1678
0070 #define PCI_DEVICE_ID_TIGON3_5715S  0x1679
0071 #define PCI_DEVICE_ID_TIGON3_5754   0x167a
0072 #define PCI_DEVICE_ID_TIGON3_5755   0x167b
0073 #define PCI_DEVICE_ID_TIGON3_5751M  0x167d
0074 #define PCI_DEVICE_ID_TIGON3_5751F  0x167e
0075 #define PCI_DEVICE_ID_TIGON3_5787F  0x167f
0076 #define PCI_DEVICE_ID_TIGON3_5761E  0x1680
0077 #define PCI_DEVICE_ID_TIGON3_5761   0x1681
0078 #define PCI_DEVICE_ID_TIGON3_5764   0x1684
0079 #define PCI_DEVICE_ID_TIGON3_5787M  0x1693
0080 #define PCI_DEVICE_ID_TIGON3_5782   0x1696
0081 #define PCI_DEVICE_ID_TIGON3_5784   0x1698
0082 #define PCI_DEVICE_ID_TIGON3_5786   0x169a
0083 #define PCI_DEVICE_ID_TIGON3_5787   0x169b
0084 #define PCI_DEVICE_ID_TIGON3_5788   0x169c
0085 #define PCI_DEVICE_ID_TIGON3_5789   0x169d
0086 #define PCI_DEVICE_ID_TIGON3_5702X  0x16a6
0087 #define PCI_DEVICE_ID_TIGON3_5703X  0x16a7
0088 #define PCI_DEVICE_ID_TIGON3_5704S  0x16a8
0089 #define PCI_DEVICE_ID_NX2_5706S     0x16aa
0090 #define PCI_DEVICE_ID_NX2_5708S     0x16ac
0091 #define PCI_DEVICE_ID_TIGON3_5702A3 0x16c6
0092 #define PCI_DEVICE_ID_TIGON3_5703A3 0x16c7
0093 #define PCI_DEVICE_ID_TIGON3_5781   0x16dd
0094 #define PCI_DEVICE_ID_TIGON3_5753   0x16f7
0095 #define PCI_DEVICE_ID_TIGON3_5753M  0x16fd
0096 #define PCI_DEVICE_ID_TIGON3_5753F  0x16fe
0097 #define PCI_DEVICE_ID_TIGON3_5901   0x170d
0098 #define PCI_DEVICE_ID_BCM4401B1     0x170c
0099 #define PCI_DEVICE_ID_TIGON3_5901_2 0x170e
0100 #define PCI_DEVICE_ID_TIGON3_5906   0x1712
0101 #define PCI_DEVICE_ID_TIGON3_5906M  0x1713
0102 #define PCI_DEVICE_ID_BCM4401       0x4401
0103 #define PCI_DEVICE_ID_BCM4401B0     0x4402
0104 
0105 
0106 /* Hardware data structures and register definitions automatically
0107  * generated from RTL code. Do not modify.
0108  */
0109 
0110 /*
0111  *  tx_bd definition
0112  */
0113 struct tx_bd {
0114   u32 tx_bd_haddr_hi;
0115   u32 tx_bd_haddr_lo;
0116   u32 tx_bd_mss_nbytes;
0117 #define TX_BD_TCP6_OFF2_SHL     (14)
0118   u32 tx_bd_vlan_tag_flags;
0119 #define TX_BD_FLAGS_CONN_FAULT      (1<<0)
0120 #define TX_BD_FLAGS_TCP6_OFF0_MSK   (3<<1)
0121 #define TX_BD_FLAGS_TCP6_OFF0_SHL   (1)
0122 #define TX_BD_FLAGS_TCP_UDP_CKSUM   (1<<1)
0123 #define TX_BD_FLAGS_IP_CKSUM        (1<<2)
0124 #define TX_BD_FLAGS_VLAN_TAG        (1<<3)
0125 #define TX_BD_FLAGS_COAL_NOW        (1<<4)
0126 #define TX_BD_FLAGS_DONT_GEN_CRC    (1<<5)
0127 #define TX_BD_FLAGS_END         (1<<6)
0128 #define TX_BD_FLAGS_START       (1<<7)
0129 #define TX_BD_FLAGS_SW_OPTION_WORD  (0x1f<<8)
0130 #define TX_BD_FLAGS_TCP6_OFF4_SHL   (12)
0131 #define TX_BD_FLAGS_SW_FLAGS        (1<<13)
0132 #define TX_BD_FLAGS_SW_SNAP     (1<<14)
0133 #define TX_BD_FLAGS_SW_LSO      (1<<15)
0134 
0135 };
0136 
0137 
0138 /*
0139  *  rx_bd definition
0140  */
0141 struct rx_bd {
0142   u32 rx_bd_haddr_hi;
0143   u32 rx_bd_haddr_lo;
0144   u32 rx_bd_len;
0145   u32 rx_bd_flags;
0146 #define RX_BD_FLAGS_NOPUSH      (1<<0)
0147 #define RX_BD_FLAGS_DUMMY       (1<<1)
0148 #define RX_BD_FLAGS_END         (1<<2)
0149 #define RX_BD_FLAGS_START       (1<<3)
0150 
0151 };
0152 
0153 #define BNX2_RX_ALIGN           16
0154 
0155 /*
0156  *  status_block definition
0157  */
0158 struct status_block {
0159   u32 status_attn_bits;
0160 #define STATUS_ATTN_BITS_LINK_STATE     (1L<<0)
0161 #define STATUS_ATTN_BITS_TX_SCHEDULER_ABORT (1L<<1)
0162 #define STATUS_ATTN_BITS_TX_BD_READ_ABORT   (1L<<2)
0163 #define STATUS_ATTN_BITS_TX_BD_CACHE_ABORT  (1L<<3)
0164 #define STATUS_ATTN_BITS_TX_PROCESSOR_ABORT (1L<<4)
0165 #define STATUS_ATTN_BITS_TX_DMA_ABORT       (1L<<5)
0166 #define STATUS_ATTN_BITS_TX_PATCHUP_ABORT   (1L<<6)
0167 #define STATUS_ATTN_BITS_TX_ASSEMBLER_ABORT (1L<<7)
0168 #define STATUS_ATTN_BITS_RX_PARSER_MAC_ABORT    (1L<<8)
0169 #define STATUS_ATTN_BITS_RX_PARSER_CATCHUP_ABORT    (1L<<9)
0170 #define STATUS_ATTN_BITS_RX_MBUF_ABORT      (1L<<10)
0171 #define STATUS_ATTN_BITS_RX_LOOKUP_ABORT    (1L<<11)
0172 #define STATUS_ATTN_BITS_RX_PROCESSOR_ABORT (1L<<12)
0173 #define STATUS_ATTN_BITS_RX_V2P_ABORT       (1L<<13)
0174 #define STATUS_ATTN_BITS_RX_BD_CACHE_ABORT  (1L<<14)
0175 #define STATUS_ATTN_BITS_RX_DMA_ABORT       (1L<<15)
0176 #define STATUS_ATTN_BITS_COMPLETION_ABORT   (1L<<16)
0177 #define STATUS_ATTN_BITS_HOST_COALESCE_ABORT    (1L<<17)
0178 #define STATUS_ATTN_BITS_MAILBOX_QUEUE_ABORT    (1L<<18)
0179 #define STATUS_ATTN_BITS_CONTEXT_ABORT      (1L<<19)
0180 #define STATUS_ATTN_BITS_CMD_SCHEDULER_ABORT    (1L<<20)
0181 #define STATUS_ATTN_BITS_CMD_PROCESSOR_ABORT    (1L<<21)
0182 #define STATUS_ATTN_BITS_MGMT_PROCESSOR_ABORT   (1L<<22)
0183 #define STATUS_ATTN_BITS_MAC_ABORT      (1L<<23)
0184 #define STATUS_ATTN_BITS_TIMER_ABORT        (1L<<24)
0185 #define STATUS_ATTN_BITS_DMAE_ABORT     (1L<<25)
0186 #define STATUS_ATTN_BITS_FLSH_ABORT     (1L<<26)
0187 #define STATUS_ATTN_BITS_GRC_ABORT      (1L<<27)
0188 #define STATUS_ATTN_BITS_EPB_ERROR      (1L<<30)
0189 #define STATUS_ATTN_BITS_PARITY_ERROR       (1L<<31)
0190 
0191   u32 status_attn_bits_ack;
0192 #if defined(__BIG_ENDIAN)
0193   u16 status_tx_quick_consumer_index0;
0194   u16 status_tx_quick_consumer_index1;
0195   u16 status_tx_quick_consumer_index2;
0196   u16 status_tx_quick_consumer_index3;
0197   u16 status_rx_quick_consumer_index0;
0198   u16 status_rx_quick_consumer_index1;
0199   u16 status_rx_quick_consumer_index2;
0200   u16 status_rx_quick_consumer_index3;
0201   u16 status_rx_quick_consumer_index4;
0202   u16 status_rx_quick_consumer_index5;
0203   u16 status_rx_quick_consumer_index6;
0204   u16 status_rx_quick_consumer_index7;
0205   u16 status_rx_quick_consumer_index8;
0206   u16 status_rx_quick_consumer_index9;
0207   u16 status_rx_quick_consumer_index10;
0208   u16 status_rx_quick_consumer_index11;
0209   u16 status_rx_quick_consumer_index12;
0210   u16 status_rx_quick_consumer_index13;
0211   u16 status_rx_quick_consumer_index14;
0212   u16 status_rx_quick_consumer_index15;
0213   u16 status_completion_producer_index;
0214   u16 status_cmd_consumer_index;
0215   u16 status_idx;
0216   u8 status_unused;
0217   u8 status_blk_num;
0218 #elif defined(__LITTLE_ENDIAN)
0219   u16 status_tx_quick_consumer_index1;
0220   u16 status_tx_quick_consumer_index0;
0221   u16 status_tx_quick_consumer_index3;
0222   u16 status_tx_quick_consumer_index2;
0223   u16 status_rx_quick_consumer_index1;
0224   u16 status_rx_quick_consumer_index0;
0225   u16 status_rx_quick_consumer_index3;
0226   u16 status_rx_quick_consumer_index2;
0227   u16 status_rx_quick_consumer_index5;
0228   u16 status_rx_quick_consumer_index4;
0229   u16 status_rx_quick_consumer_index7;
0230   u16 status_rx_quick_consumer_index6;
0231   u16 status_rx_quick_consumer_index9;
0232   u16 status_rx_quick_consumer_index8;
0233   u16 status_rx_quick_consumer_index11;
0234   u16 status_rx_quick_consumer_index10;
0235   u16 status_rx_quick_consumer_index13;
0236   u16 status_rx_quick_consumer_index12;
0237   u16 status_rx_quick_consumer_index15;
0238   u16 status_rx_quick_consumer_index14;
0239   u16 status_cmd_consumer_index;
0240   u16 status_completion_producer_index;
0241   u8 status_blk_num;
0242   u8 status_unused;
0243   u16 status_idx;
0244 #endif
0245 };
0246 
0247 /*
0248  *  status_block definition
0249  */
0250 struct status_block_msix {
0251 #if defined(__BIG_ENDIAN)
0252   u16 status_tx_quick_consumer_index;
0253   u16 status_rx_quick_consumer_index;
0254   u16 status_completion_producer_index;
0255   u16 status_cmd_consumer_index;
0256   u32 status_unused;
0257   u16 status_idx;
0258   u8 status_unused2;
0259   u8 status_blk_num;
0260 #elif defined(__LITTLE_ENDIAN)
0261   u16 status_rx_quick_consumer_index;
0262   u16 status_tx_quick_consumer_index;
0263   u16 status_cmd_consumer_index;
0264   u16 status_completion_producer_index;
0265   u32 status_unused;
0266   u8 status_blk_num;
0267   u8 status_unused2;
0268   u16 status_idx;
0269 #endif
0270 };
0271 
0272 #define BNX2_SBLK_MSIX_ALIGN_SIZE   128
0273 
0274 
0275 /*
0276  *  statistics_block definition
0277  */
0278 struct statistics_block {
0279   u32 stat_IfHCInOctets_hi;
0280   u32 stat_IfHCInOctets_lo;
0281   u32 stat_IfHCInBadOctets_hi;
0282   u32 stat_IfHCInBadOctets_lo;
0283   u32 stat_IfHCOutOctets_hi;
0284   u32 stat_IfHCOutOctets_lo;
0285   u32 stat_IfHCOutBadOctets_hi;
0286   u32 stat_IfHCOutBadOctets_lo;
0287   u32 stat_IfHCInUcastPkts_hi;
0288   u32 stat_IfHCInUcastPkts_lo;
0289   u32 stat_IfHCInMulticastPkts_hi;
0290   u32 stat_IfHCInMulticastPkts_lo;
0291   u32 stat_IfHCInBroadcastPkts_hi;
0292   u32 stat_IfHCInBroadcastPkts_lo;
0293   u32 stat_IfHCOutUcastPkts_hi;
0294   u32 stat_IfHCOutUcastPkts_lo;
0295   u32 stat_IfHCOutMulticastPkts_hi;
0296   u32 stat_IfHCOutMulticastPkts_lo;
0297   u32 stat_IfHCOutBroadcastPkts_hi;
0298   u32 stat_IfHCOutBroadcastPkts_lo;
0299   u32 stat_emac_tx_stat_dot3statsinternalmactransmiterrors;
0300   u32 stat_Dot3StatsCarrierSenseErrors;
0301   u32 stat_Dot3StatsFCSErrors;
0302   u32 stat_Dot3StatsAlignmentErrors;
0303   u32 stat_Dot3StatsSingleCollisionFrames;
0304   u32 stat_Dot3StatsMultipleCollisionFrames;
0305   u32 stat_Dot3StatsDeferredTransmissions;
0306   u32 stat_Dot3StatsExcessiveCollisions;
0307   u32 stat_Dot3StatsLateCollisions;
0308   u32 stat_EtherStatsCollisions;
0309   u32 stat_EtherStatsFragments;
0310   u32 stat_EtherStatsJabbers;
0311   u32 stat_EtherStatsUndersizePkts;
0312   u32 stat_EtherStatsOverrsizePkts;
0313   u32 stat_EtherStatsPktsRx64Octets;
0314   u32 stat_EtherStatsPktsRx65Octetsto127Octets;
0315   u32 stat_EtherStatsPktsRx128Octetsto255Octets;
0316   u32 stat_EtherStatsPktsRx256Octetsto511Octets;
0317   u32 stat_EtherStatsPktsRx512Octetsto1023Octets;
0318   u32 stat_EtherStatsPktsRx1024Octetsto1522Octets;
0319   u32 stat_EtherStatsPktsRx1523Octetsto9022Octets;
0320   u32 stat_EtherStatsPktsTx64Octets;
0321   u32 stat_EtherStatsPktsTx65Octetsto127Octets;
0322   u32 stat_EtherStatsPktsTx128Octetsto255Octets;
0323   u32 stat_EtherStatsPktsTx256Octetsto511Octets;
0324   u32 stat_EtherStatsPktsTx512Octetsto1023Octets;
0325   u32 stat_EtherStatsPktsTx1024Octetsto1522Octets;
0326   u32 stat_EtherStatsPktsTx1523Octetsto9022Octets;
0327   u32 stat_XonPauseFramesReceived;
0328   u32 stat_XoffPauseFramesReceived;
0329   u32 stat_OutXonSent;
0330   u32 stat_OutXoffSent;
0331   u32 stat_FlowControlDone;
0332   u32 stat_MacControlFramesReceived;
0333   u32 stat_XoffStateEntered;
0334   u32 stat_IfInFramesL2FilterDiscards;
0335   u32 stat_IfInRuleCheckerDiscards;
0336   u32 stat_IfInFTQDiscards;
0337   u32 stat_IfInMBUFDiscards;
0338   u32 stat_IfInRuleCheckerP4Hit;
0339   u32 stat_CatchupInRuleCheckerDiscards;
0340   u32 stat_CatchupInFTQDiscards;
0341   u32 stat_CatchupInMBUFDiscards;
0342   u32 stat_CatchupInRuleCheckerP4Hit;
0343   u32 stat_GenStat00;
0344   u32 stat_GenStat01;
0345   u32 stat_GenStat02;
0346   u32 stat_GenStat03;
0347   u32 stat_GenStat04;
0348   u32 stat_GenStat05;
0349   u32 stat_GenStat06;
0350   u32 stat_GenStat07;
0351   u32 stat_GenStat08;
0352   u32 stat_GenStat09;
0353   u32 stat_GenStat10;
0354   u32 stat_GenStat11;
0355   u32 stat_GenStat12;
0356   u32 stat_GenStat13;
0357   u32 stat_GenStat14;
0358   u32 stat_GenStat15;
0359   u32 stat_FwRxDrop;
0360 };
0361 
0362 
0363 /*
0364  *  l2_fhdr definition
0365  */
0366 struct l2_fhdr {
0367   u32 l2_fhdr_status;
0368 #define L2_FHDR_STATUS_RULE_CLASS   (0x7<<0)
0369 #define L2_FHDR_STATUS_RULE_P2      (1<<3)
0370 #define L2_FHDR_STATUS_RULE_P3      (1<<4)
0371 #define L2_FHDR_STATUS_RULE_P4      (1<<5)
0372 #define L2_FHDR_STATUS_L2_VLAN_TAG  (1<<6)
0373 #define L2_FHDR_STATUS_L2_LLC_SNAP  (1<<7)
0374 #define L2_FHDR_STATUS_RSS_HASH     (1<<8)
0375 #define L2_FHDR_STATUS_IP_DATAGRAM  (1<<13)
0376 #define L2_FHDR_STATUS_TCP_SEGMENT  (1<<14)
0377 #define L2_FHDR_STATUS_UDP_DATAGRAM (1<<15)
0378 
0379 #define L2_FHDR_STATUS_SPLIT        (1<<16)
0380 #define L2_FHDR_ERRORS_BAD_CRC      (1<<17)
0381 #define L2_FHDR_ERRORS_PHY_DECODE   (1<<18)
0382 #define L2_FHDR_ERRORS_ALIGNMENT    (1<<19)
0383 #define L2_FHDR_ERRORS_TOO_SHORT    (1<<20)
0384 #define L2_FHDR_ERRORS_GIANT_FRAME  (1<<21)
0385 #define L2_FHDR_ERRORS_TCP_XSUM     (1<<28)
0386 #define L2_FHDR_ERRORS_UDP_XSUM     (1<<31)
0387 
0388 #define L2_FHDR_STATUS_USE_RXHASH                               \
0389   (L2_FHDR_STATUS_TCP_SEGMENT | L2_FHDR_STATUS_RSS_HASH)
0390 
0391   u32 l2_fhdr_hash;
0392 #if defined(__BIG_ENDIAN)
0393   u16 l2_fhdr_pkt_len;
0394   u16 l2_fhdr_vlan_tag;
0395   u16 l2_fhdr_ip_xsum;
0396   u16 l2_fhdr_tcp_udp_xsum;
0397 #elif defined(__LITTLE_ENDIAN)
0398   u16 l2_fhdr_vlan_tag;
0399   u16 l2_fhdr_pkt_len;
0400   u16 l2_fhdr_tcp_udp_xsum;
0401   u16 l2_fhdr_ip_xsum;
0402 #endif
0403 };
0404 
0405 #define BNX2_RX_OFFSET      (sizeof(struct l2_fhdr) + 2)
0406 
0407 /*
0408  *  l2_context definition
0409  */
0410 #define BNX2_L2CTX_TYPE                 0x00000000
0411 #define BNX2_L2CTX_TYPE_SIZE_L2                          ((0xc0/0x20)<<16)
0412 #define BNX2_L2CTX_TYPE_TYPE                             (0xf<<28)
0413 #define BNX2_L2CTX_TYPE_TYPE_EMPTY                       (0<<28)
0414 #define BNX2_L2CTX_TYPE_TYPE_L2                          (1<<28)
0415 
0416 #define BNX2_L2CTX_TX_HOST_BIDX             0x00000088
0417 #define BNX2_L2CTX_EST_NBD              0x00000088
0418 #define BNX2_L2CTX_CMD_TYPE             0x00000088
0419 #define BNX2_L2CTX_CMD_TYPE_TYPE                         (0xf<<24)
0420 #define BNX2_L2CTX_CMD_TYPE_TYPE_L2                      (0<<24)
0421 #define BNX2_L2CTX_CMD_TYPE_TYPE_TCP                     (1<<24)
0422 
0423 #define BNX2_L2CTX_TX_HOST_BSEQ             0x00000090
0424 #define BNX2_L2CTX_TSCH_BSEQ                0x00000094
0425 #define BNX2_L2CTX_TBDR_BSEQ                0x00000098
0426 #define BNX2_L2CTX_TBDR_BOFF                0x0000009c
0427 #define BNX2_L2CTX_TBDR_BIDX                0x0000009c
0428 #define BNX2_L2CTX_TBDR_BHADDR_HI           0x000000a0
0429 #define BNX2_L2CTX_TBDR_BHADDR_LO           0x000000a4
0430 #define BNX2_L2CTX_TXP_BOFF             0x000000a8
0431 #define BNX2_L2CTX_TXP_BIDX             0x000000a8
0432 #define BNX2_L2CTX_TXP_BSEQ             0x000000ac
0433 
0434 #define BNX2_L2CTX_TYPE_XI              0x00000080
0435 #define BNX2_L2CTX_CMD_TYPE_XI              0x00000240
0436 #define BNX2_L2CTX_TBDR_BHADDR_HI_XI            0x00000258
0437 #define BNX2_L2CTX_TBDR_BHADDR_LO_XI            0x0000025c
0438 
0439 /*
0440  *  l2_bd_chain_context definition
0441  */
0442 #define BNX2_L2CTX_BD_PRE_READ              0x00000000
0443 #define BNX2_L2CTX_CTX_SIZE             0x00000000
0444 #define BNX2_L2CTX_CTX_TYPE             0x00000000
0445 #define BNX2_L2CTX_LO_WATER_MARK_DEFAULT                 4
0446 #define BNX2_L2CTX_LO_WATER_MARK_SCALE                   4
0447 #define BNX2_L2CTX_LO_WATER_MARK_DIS                     0
0448 #define BNX2_L2CTX_HI_WATER_MARK_SHIFT                   4
0449 #define BNX2_L2CTX_HI_WATER_MARK_SCALE                   16
0450 #define BNX2_L2CTX_WATER_MARKS_MSK                       0x000000ff
0451 #define BNX2_L2CTX_CTX_TYPE_SIZE_L2                      ((0x20/20)<<16)
0452 #define BNX2_L2CTX_CTX_TYPE_CTX_BD_CHN_TYPE              (0xf<<28)
0453 #define BNX2_L2CTX_CTX_TYPE_CTX_BD_CHN_TYPE_UNDEFINED    (0<<28)
0454 #define BNX2_L2CTX_CTX_TYPE_CTX_BD_CHN_TYPE_VALUE        (1<<28)
0455 
0456 #define BNX2_L2CTX_HOST_BDIDX               0x00000004
0457 #define BNX2_L2CTX_L5_STATUSB_NUM_SHIFT                  16
0458 #define BNX2_L2CTX_L2_STATUSB_NUM_SHIFT                  24
0459 #define BNX2_L2CTX_L5_STATUSB_NUM(sb_id)                                \
0460   (((sb_id) > 0) ? (((sb_id) + 7) << BNX2_L2CTX_L5_STATUSB_NUM_SHIFT) : 0)
0461 #define BNX2_L2CTX_L2_STATUSB_NUM(sb_id)                                \
0462   (((sb_id) > 0) ? (((sb_id) + 7) << BNX2_L2CTX_L2_STATUSB_NUM_SHIFT) : 0)
0463 #define BNX2_L2CTX_HOST_BSEQ                0x00000008
0464 #define BNX2_L2CTX_NX_BSEQ              0x0000000c
0465 #define BNX2_L2CTX_NX_BDHADDR_HI            0x00000010
0466 #define BNX2_L2CTX_NX_BDHADDR_LO            0x00000014
0467 #define BNX2_L2CTX_NX_BDIDX             0x00000018
0468 
0469 #define BNX2_L2CTX_HOST_PG_BDIDX            0x00000044
0470 #define BNX2_L2CTX_PG_BUF_SIZE              0x00000048
0471 #define BNX2_L2CTX_RBDC_KEY             0x0000004c
0472 #define BNX2_L2CTX_RBDC_JUMBO_KEY                        0x3ffe
0473 #define BNX2_L2CTX_NX_PG_BDHADDR_HI         0x00000050
0474 #define BNX2_L2CTX_NX_PG_BDHADDR_LO         0x00000054
0475 
0476 /*
0477  *  pci_config_l definition
0478  *  offset: 0000
0479  */
0480 #define BNX2_PCICFG_MSI_CONTROL             0x00000058
0481 #define BNX2_PCICFG_MSI_CONTROL_ENABLE                   (1L<<16)
0482 
0483 #define BNX2_PCICFG_MISC_CONFIG             0x00000068
0484 #define BNX2_PCICFG_MISC_CONFIG_TARGET_BYTE_SWAP         (1L<<2)
0485 #define BNX2_PCICFG_MISC_CONFIG_TARGET_MB_WORD_SWAP      (1L<<3)
0486 #define BNX2_PCICFG_MISC_CONFIG_RESERVED1                (1L<<4)
0487 #define BNX2_PCICFG_MISC_CONFIG_CLOCK_CTL_ENA            (1L<<5)
0488 #define BNX2_PCICFG_MISC_CONFIG_TARGET_GRC_WORD_SWAP     (1L<<6)
0489 #define BNX2_PCICFG_MISC_CONFIG_REG_WINDOW_ENA           (1L<<7)
0490 #define BNX2_PCICFG_MISC_CONFIG_CORE_RST_REQ             (1L<<8)
0491 #define BNX2_PCICFG_MISC_CONFIG_CORE_RST_BSY             (1L<<9)
0492 #define BNX2_PCICFG_MISC_CONFIG_GRC_WIN1_SWAP_EN         (1L<<10)
0493 #define BNX2_PCICFG_MISC_CONFIG_GRC_WIN2_SWAP_EN         (1L<<11)
0494 #define BNX2_PCICFG_MISC_CONFIG_GRC_WIN3_SWAP_EN         (1L<<12)
0495 #define BNX2_PCICFG_MISC_CONFIG_ASIC_METAL_REV           (0xffL<<16)
0496 #define BNX2_PCICFG_MISC_CONFIG_ASIC_BASE_REV            (0xfL<<24)
0497 #define BNX2_PCICFG_MISC_CONFIG_ASIC_ID                  (0xfL<<28)
0498 
0499 #define BNX2_PCICFG_MISC_STATUS             0x0000006c
0500 #define BNX2_PCICFG_MISC_STATUS_INTA_VALUE               (1L<<0)
0501 #define BNX2_PCICFG_MISC_STATUS_32BIT_DET                (1L<<1)
0502 #define BNX2_PCICFG_MISC_STATUS_M66EN                    (1L<<2)
0503 #define BNX2_PCICFG_MISC_STATUS_PCIX_DET                 (1L<<3)
0504 #define BNX2_PCICFG_MISC_STATUS_PCIX_SPEED               (0x3L<<4)
0505 #define BNX2_PCICFG_MISC_STATUS_PCIX_SPEED_66            (0L<<4)
0506 #define BNX2_PCICFG_MISC_STATUS_PCIX_SPEED_100           (1L<<4)
0507 #define BNX2_PCICFG_MISC_STATUS_PCIX_SPEED_133           (2L<<4)
0508 #define BNX2_PCICFG_MISC_STATUS_PCIX_SPEED_PCI_MODE      (3L<<4)
0509 #define BNX2_PCICFG_MISC_STATUS_BAD_MEM_WRITE_BE         (1L<<8)
0510 
0511 #define BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS      0x00000070
0512 #define BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET       (0xfL<<0)
0513 #define BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_32MHZ         (0L<<0)
0514 #define BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_38MHZ         (1L<<0)
0515 #define BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_48MHZ         (2L<<0)
0516 #define BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_55MHZ         (3L<<0)
0517 #define BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_66MHZ         (4L<<0)
0518 #define BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_80MHZ         (5L<<0)
0519 #define BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_95MHZ         (6L<<0)
0520 #define BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_133MHZ        (7L<<0)
0521 #define BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_LOW   (0xfL<<0)
0522 #define BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_CORE_CLK_DISABLE      (1L<<6)
0523 #define BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_CORE_CLK_ALT  (1L<<7)
0524 #define BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_CORE_CLK_ALT_SRC      (0x7L<<8)
0525 #define BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_CORE_CLK_ALT_SRC_UNDEF        (0L<<8)
0526 #define BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_CORE_CLK_ALT_SRC_12   (1L<<8)
0527 #define BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_CORE_CLK_ALT_SRC_6    (2L<<8)
0528 #define BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_CORE_CLK_ALT_SRC_62   (4L<<8)
0529 #define BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_MIN_POWER     (1L<<11)
0530 #define BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_CORE_CLK_PLL_SPEED    (0xfL<<12)
0531 #define BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_CORE_CLK_PLL_SPEED_100        (0L<<12)
0532 #define BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_CORE_CLK_PLL_SPEED_80         (1L<<12)
0533 #define BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_CORE_CLK_PLL_SPEED_50         (2L<<12)
0534 #define BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_CORE_CLK_PLL_SPEED_40         (4L<<12)
0535 #define BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_CORE_CLK_PLL_SPEED_25         (8L<<12)
0536 #define BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_CORE_CLK_PLL_STOP     (1L<<16)
0537 #define BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_RESERVED_17   (1L<<17)
0538 #define BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_RESERVED_18   (1L<<18)
0539 #define BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_RESERVED_19   (1L<<19)
0540 #define BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_RESERVED      (0xfffL<<20)
0541 
0542 #define BNX2_PCICFG_REG_WINDOW_ADDRESS          0x00000078
0543 #define BNX2_PCICFG_REG_WINDOW_ADDRESS_VAL               (0xfffffL<<2)
0544 
0545 #define BNX2_PCICFG_REG_WINDOW              0x00000080
0546 #define BNX2_PCICFG_INT_ACK_CMD             0x00000084
0547 #define BNX2_PCICFG_INT_ACK_CMD_INDEX                    (0xffffL<<0)
0548 #define BNX2_PCICFG_INT_ACK_CMD_INDEX_VALID              (1L<<16)
0549 #define BNX2_PCICFG_INT_ACK_CMD_USE_INT_HC_PARAM         (1L<<17)
0550 #define BNX2_PCICFG_INT_ACK_CMD_MASK_INT                 (1L<<18)
0551 #define BNX2_PCICFG_INT_ACK_CMD_INTERRUPT_NUM            (0xfL<<24)
0552 #define BNX2_PCICFG_INT_ACK_CMD_INT_NUM_SHIFT            24
0553 
0554 #define BNX2_PCICFG_STATUS_BIT_SET_CMD          0x00000088
0555 #define BNX2_PCICFG_STATUS_BIT_CLEAR_CMD        0x0000008c
0556 #define BNX2_PCICFG_MAILBOX_QUEUE_ADDR          0x00000090
0557 #define BNX2_PCICFG_MAILBOX_QUEUE_DATA          0x00000094
0558 
0559 
0560 /*
0561  *  pci_reg definition
0562  *  offset: 0x400
0563  */
0564 #define BNX2_PCI_GRC_WINDOW_ADDR            0x00000400
0565 #define BNX2_PCI_GRC_WINDOW_ADDR_VALUE                   (0x1ffL<<13)
0566 #define BNX2_PCI_GRC_WINDOW_ADDR_SEP_WIN                 (1L<<31)
0567 
0568 #define BNX2_PCI_GRC_WINDOW2_BASE                        0xc000
0569 #define BNX2_PCI_GRC_WINDOW3_BASE                        0xe000
0570 
0571 #define BNX2_PCI_CONFIG_1               0x00000404
0572 #define BNX2_PCI_CONFIG_1_RESERVED0                      (0xffL<<0)
0573 #define BNX2_PCI_CONFIG_1_READ_BOUNDARY                  (0x7L<<8)
0574 #define BNX2_PCI_CONFIG_1_READ_BOUNDARY_OFF              (0L<<8)
0575 #define BNX2_PCI_CONFIG_1_READ_BOUNDARY_16               (1L<<8)
0576 #define BNX2_PCI_CONFIG_1_READ_BOUNDARY_32               (2L<<8)
0577 #define BNX2_PCI_CONFIG_1_READ_BOUNDARY_64               (3L<<8)
0578 #define BNX2_PCI_CONFIG_1_READ_BOUNDARY_128              (4L<<8)
0579 #define BNX2_PCI_CONFIG_1_READ_BOUNDARY_256              (5L<<8)
0580 #define BNX2_PCI_CONFIG_1_READ_BOUNDARY_512              (6L<<8)
0581 #define BNX2_PCI_CONFIG_1_READ_BOUNDARY_1024             (7L<<8)
0582 #define BNX2_PCI_CONFIG_1_WRITE_BOUNDARY                 (0x7L<<11)
0583 #define BNX2_PCI_CONFIG_1_WRITE_BOUNDARY_OFF             (0L<<11)
0584 #define BNX2_PCI_CONFIG_1_WRITE_BOUNDARY_16              (1L<<11)
0585 #define BNX2_PCI_CONFIG_1_WRITE_BOUNDARY_32              (2L<<11)
0586 #define BNX2_PCI_CONFIG_1_WRITE_BOUNDARY_64              (3L<<11)
0587 #define BNX2_PCI_CONFIG_1_WRITE_BOUNDARY_128             (4L<<11)
0588 #define BNX2_PCI_CONFIG_1_WRITE_BOUNDARY_256             (5L<<11)
0589 #define BNX2_PCI_CONFIG_1_WRITE_BOUNDARY_512             (6L<<11)
0590 #define BNX2_PCI_CONFIG_1_WRITE_BOUNDARY_1024            (7L<<11)
0591 #define BNX2_PCI_CONFIG_1_RESERVED1                      (0x3ffffL<<14)
0592 
0593 #define BNX2_PCI_CONFIG_2               0x00000408
0594 #define BNX2_PCI_CONFIG_2_BAR1_SIZE                      (0xfL<<0)
0595 #define BNX2_PCI_CONFIG_2_BAR1_SIZE_DISABLED             (0L<<0)
0596 #define BNX2_PCI_CONFIG_2_BAR1_SIZE_64K                  (1L<<0)
0597 #define BNX2_PCI_CONFIG_2_BAR1_SIZE_128K                 (2L<<0)
0598 #define BNX2_PCI_CONFIG_2_BAR1_SIZE_256K                 (3L<<0)
0599 #define BNX2_PCI_CONFIG_2_BAR1_SIZE_512K                 (4L<<0)
0600 #define BNX2_PCI_CONFIG_2_BAR1_SIZE_1M                   (5L<<0)
0601 #define BNX2_PCI_CONFIG_2_BAR1_SIZE_2M                   (6L<<0)
0602 #define BNX2_PCI_CONFIG_2_BAR1_SIZE_4M                   (7L<<0)
0603 #define BNX2_PCI_CONFIG_2_BAR1_SIZE_8M                   (8L<<0)
0604 #define BNX2_PCI_CONFIG_2_BAR1_SIZE_16M                  (9L<<0)
0605 #define BNX2_PCI_CONFIG_2_BAR1_SIZE_32M                  (10L<<0)
0606 #define BNX2_PCI_CONFIG_2_BAR1_SIZE_64M                  (11L<<0)
0607 #define BNX2_PCI_CONFIG_2_BAR1_SIZE_128M                 (12L<<0)
0608 #define BNX2_PCI_CONFIG_2_BAR1_SIZE_256M                 (13L<<0)
0609 #define BNX2_PCI_CONFIG_2_BAR1_SIZE_512M                 (14L<<0)
0610 #define BNX2_PCI_CONFIG_2_BAR1_SIZE_1G                   (15L<<0)
0611 #define BNX2_PCI_CONFIG_2_BAR1_64ENA                     (1L<<4)
0612 #define BNX2_PCI_CONFIG_2_EXP_ROM_RETRY                  (1L<<5)
0613 #define BNX2_PCI_CONFIG_2_CFG_CYCLE_RETRY                (1L<<6)
0614 #define BNX2_PCI_CONFIG_2_FIRST_CFG_DONE                 (1L<<7)
0615 #define BNX2_PCI_CONFIG_2_EXP_ROM_SIZE                   (0xffL<<8)
0616 #define BNX2_PCI_CONFIG_2_EXP_ROM_SIZE_DISABLED          (0L<<8)
0617 #define BNX2_PCI_CONFIG_2_EXP_ROM_SIZE_1K                (1L<<8)
0618 #define BNX2_PCI_CONFIG_2_EXP_ROM_SIZE_2K                (2L<<8)
0619 #define BNX2_PCI_CONFIG_2_EXP_ROM_SIZE_4K                (3L<<8)
0620 #define BNX2_PCI_CONFIG_2_EXP_ROM_SIZE_8K                (4L<<8)
0621 #define BNX2_PCI_CONFIG_2_EXP_ROM_SIZE_16K               (5L<<8)
0622 #define BNX2_PCI_CONFIG_2_EXP_ROM_SIZE_32K               (6L<<8)
0623 #define BNX2_PCI_CONFIG_2_EXP_ROM_SIZE_64K               (7L<<8)
0624 #define BNX2_PCI_CONFIG_2_EXP_ROM_SIZE_128K              (8L<<8)
0625 #define BNX2_PCI_CONFIG_2_EXP_ROM_SIZE_256K              (9L<<8)
0626 #define BNX2_PCI_CONFIG_2_EXP_ROM_SIZE_512K              (10L<<8)
0627 #define BNX2_PCI_CONFIG_2_EXP_ROM_SIZE_1M                (11L<<8)
0628 #define BNX2_PCI_CONFIG_2_EXP_ROM_SIZE_2M                (12L<<8)
0629 #define BNX2_PCI_CONFIG_2_EXP_ROM_SIZE_4M                (13L<<8)
0630 #define BNX2_PCI_CONFIG_2_EXP_ROM_SIZE_8M                (14L<<8)
0631 #define BNX2_PCI_CONFIG_2_EXP_ROM_SIZE_16M               (15L<<8)
0632 #define BNX2_PCI_CONFIG_2_MAX_SPLIT_LIMIT                (0x1fL<<16)
0633 #define BNX2_PCI_CONFIG_2_MAX_READ_LIMIT                 (0x3L<<21)
0634 #define BNX2_PCI_CONFIG_2_MAX_READ_LIMIT_512             (0L<<21)
0635 #define BNX2_PCI_CONFIG_2_MAX_READ_LIMIT_1K              (1L<<21)
0636 #define BNX2_PCI_CONFIG_2_MAX_READ_LIMIT_2K              (2L<<21)
0637 #define BNX2_PCI_CONFIG_2_MAX_READ_LIMIT_4K              (3L<<21)
0638 #define BNX2_PCI_CONFIG_2_FORCE_32_BIT_MSTR              (1L<<23)
0639 #define BNX2_PCI_CONFIG_2_FORCE_32_BIT_TGT               (1L<<24)
0640 #define BNX2_PCI_CONFIG_2_KEEP_REQ_ASSERT                (1L<<25)
0641 #define BNX2_PCI_CONFIG_2_RESERVED0                      (0x3fL<<26)
0642 #define BNX2_PCI_CONFIG_2_BAR_PREFETCH_XI                (1L<<16)
0643 #define BNX2_PCI_CONFIG_2_RESERVED0_XI                   (0x7fffL<<17)
0644 
0645 #define BNX2_PCI_CONFIG_3               0x0000040c
0646 #define BNX2_PCI_CONFIG_3_STICKY_BYTE                    (0xffL<<0)
0647 #define BNX2_PCI_CONFIG_3_REG_STICKY_BYTE                (0xffL<<8)
0648 #define BNX2_PCI_CONFIG_3_FORCE_PME                      (1L<<24)
0649 #define BNX2_PCI_CONFIG_3_PME_STATUS                     (1L<<25)
0650 #define BNX2_PCI_CONFIG_3_PME_ENABLE                     (1L<<26)
0651 #define BNX2_PCI_CONFIG_3_PM_STATE                       (0x3L<<27)
0652 #define BNX2_PCI_CONFIG_3_VAUX_PRESET                    (1L<<30)
0653 #define BNX2_PCI_CONFIG_3_PCI_POWER                      (1L<<31)
0654 
0655 #define BNX2_PCI_PM_DATA_A              0x00000410
0656 #define BNX2_PCI_PM_DATA_A_PM_DATA_0_PRG                 (0xffL<<0)
0657 #define BNX2_PCI_PM_DATA_A_PM_DATA_1_PRG                 (0xffL<<8)
0658 #define BNX2_PCI_PM_DATA_A_PM_DATA_2_PRG                 (0xffL<<16)
0659 #define BNX2_PCI_PM_DATA_A_PM_DATA_3_PRG                 (0xffL<<24)
0660 
0661 #define BNX2_PCI_PM_DATA_B              0x00000414
0662 #define BNX2_PCI_PM_DATA_B_PM_DATA_4_PRG                 (0xffL<<0)
0663 #define BNX2_PCI_PM_DATA_B_PM_DATA_5_PRG                 (0xffL<<8)
0664 #define BNX2_PCI_PM_DATA_B_PM_DATA_6_PRG                 (0xffL<<16)
0665 #define BNX2_PCI_PM_DATA_B_PM_DATA_7_PRG                 (0xffL<<24)
0666 
0667 #define BNX2_PCI_SWAP_DIAG0             0x00000418
0668 #define BNX2_PCI_SWAP_DIAG1             0x0000041c
0669 #define BNX2_PCI_EXP_ROM_ADDR               0x00000420
0670 #define BNX2_PCI_EXP_ROM_ADDR_ADDRESS                    (0x3fffffL<<2)
0671 #define BNX2_PCI_EXP_ROM_ADDR_REQ                        (1L<<31)
0672 
0673 #define BNX2_PCI_EXP_ROM_DATA               0x00000424
0674 #define BNX2_PCI_VPD_INTF               0x00000428
0675 #define BNX2_PCI_VPD_INTF_INTF_REQ                       (1L<<0)
0676 
0677 #define BNX2_PCI_VPD_ADDR_FLAG              0x0000042c
0678 #define BNX2_PCI_VPD_ADDR_FLAG_MSK          0x0000ffff
0679 #define BNX2_PCI_VPD_ADDR_FLAG_SL           0L
0680 #define BNX2_PCI_VPD_ADDR_FLAG_ADDRESS                   (0x1fffL<<2)
0681 #define BNX2_PCI_VPD_ADDR_FLAG_WR                        (1L<<15)
0682 
0683 #define BNX2_PCI_VPD_DATA               0x00000430
0684 #define BNX2_PCI_ID_VAL1                0x00000434
0685 #define BNX2_PCI_ID_VAL1_DEVICE_ID                       (0xffffL<<0)
0686 #define BNX2_PCI_ID_VAL1_VENDOR_ID                       (0xffffL<<16)
0687 
0688 #define BNX2_PCI_ID_VAL2                0x00000438
0689 #define BNX2_PCI_ID_VAL2_SUBSYSTEM_VENDOR_ID             (0xffffL<<0)
0690 #define BNX2_PCI_ID_VAL2_SUBSYSTEM_ID                    (0xffffL<<16)
0691 
0692 #define BNX2_PCI_ID_VAL3                0x0000043c
0693 #define BNX2_PCI_ID_VAL3_CLASS_CODE                      (0xffffffL<<0)
0694 #define BNX2_PCI_ID_VAL3_REVISION_ID                     (0xffL<<24)
0695 
0696 #define BNX2_PCI_ID_VAL4                0x00000440
0697 #define BNX2_PCI_ID_VAL4_CAP_ENA                         (0xfL<<0)
0698 #define BNX2_PCI_ID_VAL4_CAP_ENA_0                       (0L<<0)
0699 #define BNX2_PCI_ID_VAL4_CAP_ENA_1                       (1L<<0)
0700 #define BNX2_PCI_ID_VAL4_CAP_ENA_2                       (2L<<0)
0701 #define BNX2_PCI_ID_VAL4_CAP_ENA_3                       (3L<<0)
0702 #define BNX2_PCI_ID_VAL4_CAP_ENA_4                       (4L<<0)
0703 #define BNX2_PCI_ID_VAL4_CAP_ENA_5                       (5L<<0)
0704 #define BNX2_PCI_ID_VAL4_CAP_ENA_6                       (6L<<0)
0705 #define BNX2_PCI_ID_VAL4_CAP_ENA_7                       (7L<<0)
0706 #define BNX2_PCI_ID_VAL4_CAP_ENA_8                       (8L<<0)
0707 #define BNX2_PCI_ID_VAL4_CAP_ENA_9                       (9L<<0)
0708 #define BNX2_PCI_ID_VAL4_CAP_ENA_10                      (10L<<0)
0709 #define BNX2_PCI_ID_VAL4_CAP_ENA_11                      (11L<<0)
0710 #define BNX2_PCI_ID_VAL4_CAP_ENA_12                      (12L<<0)
0711 #define BNX2_PCI_ID_VAL4_CAP_ENA_13                      (13L<<0)
0712 #define BNX2_PCI_ID_VAL4_CAP_ENA_14                      (14L<<0)
0713 #define BNX2_PCI_ID_VAL4_CAP_ENA_15                      (15L<<0)
0714 #define BNX2_PCI_ID_VAL4_RESERVED0                       (0x3L<<4)
0715 #define BNX2_PCI_ID_VAL4_PM_SCALE_PRG                    (0x3L<<6)
0716 #define BNX2_PCI_ID_VAL4_PM_SCALE_PRG_0                  (0L<<6)
0717 #define BNX2_PCI_ID_VAL4_PM_SCALE_PRG_1                  (1L<<6)
0718 #define BNX2_PCI_ID_VAL4_PM_SCALE_PRG_2                  (2L<<6)
0719 #define BNX2_PCI_ID_VAL4_PM_SCALE_PRG_3                  (3L<<6)
0720 #define BNX2_PCI_ID_VAL4_MSI_PV_MASK_CAP                 (1L<<8)
0721 #define BNX2_PCI_ID_VAL4_MSI_LIMIT                       (0x7L<<9)
0722 #define BNX2_PCI_ID_VAL4_MULTI_MSG_CAP                   (0x7L<<12)
0723 #define BNX2_PCI_ID_VAL4_MSI_ENABLE                      (1L<<15)
0724 #define BNX2_PCI_ID_VAL4_MAX_64_ADVERTIZE                (1L<<16)
0725 #define BNX2_PCI_ID_VAL4_MAX_133_ADVERTIZE               (1L<<17)
0726 #define BNX2_PCI_ID_VAL4_RESERVED2                       (0x7L<<18)
0727 #define BNX2_PCI_ID_VAL4_MAX_CUMULATIVE_SIZE_B21         (0x3L<<21)
0728 #define BNX2_PCI_ID_VAL4_MAX_SPLIT_SIZE_B21              (0x3L<<23)
0729 #define BNX2_PCI_ID_VAL4_MAX_CUMULATIVE_SIZE_B0          (1L<<25)
0730 #define BNX2_PCI_ID_VAL4_MAX_MEM_READ_SIZE_B10           (0x3L<<26)
0731 #define BNX2_PCI_ID_VAL4_MAX_SPLIT_SIZE_B0               (1L<<28)
0732 #define BNX2_PCI_ID_VAL4_RESERVED3                       (0x7L<<29)
0733 #define BNX2_PCI_ID_VAL4_RESERVED3_XI                    (0xffffL<<16)
0734 
0735 #define BNX2_PCI_ID_VAL5                0x00000444
0736 #define BNX2_PCI_ID_VAL5_D1_SUPPORT                      (1L<<0)
0737 #define BNX2_PCI_ID_VAL5_D2_SUPPORT                      (1L<<1)
0738 #define BNX2_PCI_ID_VAL5_PME_IN_D0                       (1L<<2)
0739 #define BNX2_PCI_ID_VAL5_PME_IN_D1                       (1L<<3)
0740 #define BNX2_PCI_ID_VAL5_PME_IN_D2                       (1L<<4)
0741 #define BNX2_PCI_ID_VAL5_PME_IN_D3_HOT                   (1L<<5)
0742 #define BNX2_PCI_ID_VAL5_RESERVED0_TE                    (0x3ffffffL<<6)
0743 #define BNX2_PCI_ID_VAL5_PM_VERSION_XI                   (0x7L<<6)
0744 #define BNX2_PCI_ID_VAL5_NO_SOFT_RESET_XI                (1L<<9)
0745 #define BNX2_PCI_ID_VAL5_RESERVED0_XI                    (0x3fffffL<<10)
0746 
0747 #define BNX2_PCI_PCIX_EXTENDED_STATUS           0x00000448
0748 #define BNX2_PCI_PCIX_EXTENDED_STATUS_NO_SNOOP           (1L<<8)
0749 #define BNX2_PCI_PCIX_EXTENDED_STATUS_LONG_BURST         (1L<<9)
0750 #define BNX2_PCI_PCIX_EXTENDED_STATUS_SPLIT_COMP_MSG_CLASS       (0xfL<<16)
0751 #define BNX2_PCI_PCIX_EXTENDED_STATUS_SPLIT_COMP_MSG_IDX         (0xffL<<24)
0752 
0753 #define BNX2_PCI_ID_VAL6                0x0000044c
0754 #define BNX2_PCI_ID_VAL6_MAX_LAT                         (0xffL<<0)
0755 #define BNX2_PCI_ID_VAL6_MIN_GNT                         (0xffL<<8)
0756 #define BNX2_PCI_ID_VAL6_BIST                            (0xffL<<16)
0757 #define BNX2_PCI_ID_VAL6_RESERVED0                       (0xffL<<24)
0758 
0759 #define BNX2_PCI_MSI_DATA               0x00000450
0760 #define BNX2_PCI_MSI_DATA_MSI_DATA                       (0xffffL<<0)
0761 
0762 #define BNX2_PCI_MSI_ADDR_H             0x00000454
0763 #define BNX2_PCI_MSI_ADDR_L             0x00000458
0764 #define BNX2_PCI_MSI_ADDR_L_VAL                          (0x3fffffffL<<2)
0765 
0766 #define BNX2_PCI_CFG_ACCESS_CMD             0x0000045c
0767 #define BNX2_PCI_CFG_ACCESS_CMD_ADR                      (0x3fL<<2)
0768 #define BNX2_PCI_CFG_ACCESS_CMD_RD_REQ                   (1L<<27)
0769 #define BNX2_PCI_CFG_ACCESS_CMD_WR_REQ                   (0xfL<<28)
0770 
0771 #define BNX2_PCI_CFG_ACCESS_DATA            0x00000460
0772 #define BNX2_PCI_MSI_MASK               0x00000464
0773 #define BNX2_PCI_MSI_MASK_MSI_MASK                       (0xffffffffL<<0)
0774 
0775 #define BNX2_PCI_MSI_PEND               0x00000468
0776 #define BNX2_PCI_MSI_PEND_MSI_PEND                       (0xffffffffL<<0)
0777 
0778 #define BNX2_PCI_PM_DATA_C              0x0000046c
0779 #define BNX2_PCI_PM_DATA_C_PM_DATA_8_PRG                 (0xffL<<0)
0780 #define BNX2_PCI_PM_DATA_C_RESERVED0                     (0xffffffL<<8)
0781 
0782 #define BNX2_PCI_MSIX_CONTROL               0x000004c0
0783 #define BNX2_PCI_MSIX_CONTROL_MSIX_TBL_SIZ               (0x7ffL<<0)
0784 #define BNX2_PCI_MSIX_CONTROL_RESERVED0                  (0x1fffffL<<11)
0785 
0786 #define BNX2_PCI_MSIX_TBL_OFF_BIR           0x000004c4
0787 #define BNX2_PCI_MSIX_TBL_OFF_BIR_MSIX_TBL_BIR           (0x7L<<0)
0788 #define BNX2_PCI_MSIX_TBL_OFF_BIR_MSIX_TBL_OFF           (0x1fffffffL<<3)
0789 
0790 #define BNX2_PCI_MSIX_PBA_OFF_BIT           0x000004c8
0791 #define BNX2_PCI_MSIX_PBA_OFF_BIT_MSIX_PBA_BIR           (0x7L<<0)
0792 #define BNX2_PCI_MSIX_PBA_OFF_BIT_MSIX_PBA_OFF           (0x1fffffffL<<3)
0793 
0794 #define BNX2_PCI_PCIE_CAPABILITY            0x000004d0
0795 #define BNX2_PCI_PCIE_CAPABILITY_INTERRUPT_MSG_NUM       (0x1fL<<0)
0796 #define BNX2_PCI_PCIE_CAPABILITY_COMPLY_PCIE_1_1         (1L<<5)
0797 
0798 #define BNX2_PCI_DEVICE_CAPABILITY          0x000004d4
0799 #define BNX2_PCI_DEVICE_CAPABILITY_MAX_PL_SIZ_SUPPORTED  (0x7L<<0)
0800 #define BNX2_PCI_DEVICE_CAPABILITY_EXTENDED_TAG_SUPPORT  (1L<<5)
0801 #define BNX2_PCI_DEVICE_CAPABILITY_L0S_ACCEPTABLE_LATENCY        (0x7L<<6)
0802 #define BNX2_PCI_DEVICE_CAPABILITY_L1_ACCEPTABLE_LATENCY         (0x7L<<9)
0803 #define BNX2_PCI_DEVICE_CAPABILITY_ROLE_BASED_ERR_RPT    (1L<<15)
0804 
0805 #define BNX2_PCI_LINK_CAPABILITY            0x000004dc
0806 #define BNX2_PCI_LINK_CAPABILITY_MAX_LINK_SPEED          (0xfL<<0)
0807 #define BNX2_PCI_LINK_CAPABILITY_MAX_LINK_SPEED_0001     (1L<<0)
0808 #define BNX2_PCI_LINK_CAPABILITY_MAX_LINK_SPEED_0010     (1L<<0)
0809 #define BNX2_PCI_LINK_CAPABILITY_MAX_LINK_WIDTH          (0x1fL<<4)
0810 #define BNX2_PCI_LINK_CAPABILITY_CLK_POWER_MGMT          (1L<<9)
0811 #define BNX2_PCI_LINK_CAPABILITY_ASPM_SUPPORT            (0x3L<<10)
0812 #define BNX2_PCI_LINK_CAPABILITY_L0S_EXIT_LAT            (0x7L<<12)
0813 #define BNX2_PCI_LINK_CAPABILITY_L0S_EXIT_LAT_101        (5L<<12)
0814 #define BNX2_PCI_LINK_CAPABILITY_L0S_EXIT_LAT_110        (6L<<12)
0815 #define BNX2_PCI_LINK_CAPABILITY_L1_EXIT_LAT             (0x7L<<15)
0816 #define BNX2_PCI_LINK_CAPABILITY_L1_EXIT_LAT_001         (1L<<15)
0817 #define BNX2_PCI_LINK_CAPABILITY_L1_EXIT_LAT_010         (2L<<15)
0818 #define BNX2_PCI_LINK_CAPABILITY_L0S_EXIT_COMM_LAT       (0x7L<<18)
0819 #define BNX2_PCI_LINK_CAPABILITY_L0S_EXIT_COMM_LAT_101   (5L<<18)
0820 #define BNX2_PCI_LINK_CAPABILITY_L0S_EXIT_COMM_LAT_110   (6L<<18)
0821 #define BNX2_PCI_LINK_CAPABILITY_L1_EXIT_COMM_LAT        (0x7L<<21)
0822 #define BNX2_PCI_LINK_CAPABILITY_L1_EXIT_COMM_LAT_001    (1L<<21)
0823 #define BNX2_PCI_LINK_CAPABILITY_L1_EXIT_COMM_LAT_010    (2L<<21)
0824 #define BNX2_PCI_LINK_CAPABILITY_PORT_NUM                (0xffL<<24)
0825 
0826 #define BNX2_PCI_PCIE_DEVICE_CAPABILITY_2       0x000004e4
0827 #define BNX2_PCI_PCIE_DEVICE_CAPABILITY_2_CMPL_TO_RANGE_SUPP     (0xfL<<0)
0828 #define BNX2_PCI_PCIE_DEVICE_CAPABILITY_2_CMPL_TO_DISABL_SUPP    (1L<<4)
0829 #define BNX2_PCI_PCIE_DEVICE_CAPABILITY_2_RESERVED       (0x7ffffffL<<5)
0830 
0831 #define BNX2_PCI_PCIE_LINK_CAPABILITY_2         0x000004e8
0832 #define BNX2_PCI_PCIE_LINK_CAPABILITY_2_RESERVED         (0xffffffffL<<0)
0833 
0834 #define BNX2_PCI_GRC_WINDOW1_ADDR           0x00000610
0835 #define BNX2_PCI_GRC_WINDOW1_ADDR_VALUE                  (0x1ffL<<13)
0836 
0837 #define BNX2_PCI_GRC_WINDOW2_ADDR           0x00000614
0838 #define BNX2_PCI_GRC_WINDOW2_ADDR_VALUE                  (0x1ffL<<13)
0839 
0840 #define BNX2_PCI_GRC_WINDOW3_ADDR           0x00000618
0841 #define BNX2_PCI_GRC_WINDOW3_ADDR_VALUE                  (0x1ffL<<13)
0842 
0843 #define BNX2_MSIX_TABLE_ADDR                             0x318000
0844 #define BNX2_MSIX_PBA_ADDR                               0x31c000
0845 
0846 /*
0847  *  misc_reg definition
0848  *  offset: 0x800
0849  */
0850 #define BNX2_MISC_COMMAND               0x00000800
0851 #define BNX2_MISC_COMMAND_ENABLE_ALL                     (1L<<0)
0852 #define BNX2_MISC_COMMAND_DISABLE_ALL                    (1L<<1)
0853 #define BNX2_MISC_COMMAND_SW_RESET                       (1L<<4)
0854 #define BNX2_MISC_COMMAND_POR_RESET                      (1L<<5)
0855 #define BNX2_MISC_COMMAND_HD_RESET                       (1L<<6)
0856 #define BNX2_MISC_COMMAND_CMN_SW_RESET                   (1L<<7)
0857 #define BNX2_MISC_COMMAND_PAR_ERROR                      (1L<<8)
0858 #define BNX2_MISC_COMMAND_CS16_ERR                       (1L<<9)
0859 #define BNX2_MISC_COMMAND_CS16_ERR_LOC                   (0xfL<<12)
0860 #define BNX2_MISC_COMMAND_PAR_ERR_RAM                    (0x7fL<<16)
0861 #define BNX2_MISC_COMMAND_POWERDOWN_EVENT                (1L<<23)
0862 #define BNX2_MISC_COMMAND_SW_SHUTDOWN                    (1L<<24)
0863 #define BNX2_MISC_COMMAND_SHUTDOWN_EN                    (1L<<25)
0864 #define BNX2_MISC_COMMAND_DINTEG_ATTN_EN                 (1L<<26)
0865 #define BNX2_MISC_COMMAND_PCIE_LINK_IN_L23               (1L<<27)
0866 #define BNX2_MISC_COMMAND_PCIE_DIS                       (1L<<28)
0867 
0868 #define BNX2_MISC_CFG                   0x00000804
0869 #define BNX2_MISC_CFG_GRC_TMOUT                          (1L<<0)
0870 #define BNX2_MISC_CFG_NVM_WR_EN                          (0x3L<<1)
0871 #define BNX2_MISC_CFG_NVM_WR_EN_PROTECT                  (0L<<1)
0872 #define BNX2_MISC_CFG_NVM_WR_EN_PCI                      (1L<<1)
0873 #define BNX2_MISC_CFG_NVM_WR_EN_ALLOW                    (2L<<1)
0874 #define BNX2_MISC_CFG_NVM_WR_EN_ALLOW2                   (3L<<1)
0875 #define BNX2_MISC_CFG_BIST_EN                            (1L<<3)
0876 #define BNX2_MISC_CFG_CK25_OUT_ALT_SRC                   (1L<<4)
0877 #define BNX2_MISC_CFG_RESERVED5_TE                       (1L<<5)
0878 #define BNX2_MISC_CFG_RESERVED6_TE                       (1L<<6)
0879 #define BNX2_MISC_CFG_CLK_CTL_OVERRIDE                   (1L<<7)
0880 #define BNX2_MISC_CFG_LEDMODE                            (0x7L<<8)
0881 #define BNX2_MISC_CFG_LEDMODE_MAC                        (0L<<8)
0882 #define BNX2_MISC_CFG_LEDMODE_PHY1_TE                    (1L<<8)
0883 #define BNX2_MISC_CFG_LEDMODE_PHY2_TE                    (2L<<8)
0884 #define BNX2_MISC_CFG_LEDMODE_PHY3_TE                    (3L<<8)
0885 #define BNX2_MISC_CFG_LEDMODE_PHY4_TE                    (4L<<8)
0886 #define BNX2_MISC_CFG_LEDMODE_PHY5_TE                    (5L<<8)
0887 #define BNX2_MISC_CFG_LEDMODE_PHY6_TE                    (6L<<8)
0888 #define BNX2_MISC_CFG_LEDMODE_PHY7_TE                    (7L<<8)
0889 #define BNX2_MISC_CFG_MCP_GRC_TMOUT_TE                   (1L<<11)
0890 #define BNX2_MISC_CFG_DBU_GRC_TMOUT_TE                   (1L<<12)
0891 #define BNX2_MISC_CFG_LEDMODE_XI                         (0xfL<<8)
0892 #define BNX2_MISC_CFG_LEDMODE_MAC_XI                     (0L<<8)
0893 #define BNX2_MISC_CFG_LEDMODE_PHY1_XI                    (1L<<8)
0894 #define BNX2_MISC_CFG_LEDMODE_PHY2_XI                    (2L<<8)
0895 #define BNX2_MISC_CFG_LEDMODE_PHY3_XI                    (3L<<8)
0896 #define BNX2_MISC_CFG_LEDMODE_MAC2_XI                    (4L<<8)
0897 #define BNX2_MISC_CFG_LEDMODE_PHY4_XI                    (5L<<8)
0898 #define BNX2_MISC_CFG_LEDMODE_PHY5_XI                    (6L<<8)
0899 #define BNX2_MISC_CFG_LEDMODE_PHY6_XI                    (7L<<8)
0900 #define BNX2_MISC_CFG_LEDMODE_MAC3_XI                    (8L<<8)
0901 #define BNX2_MISC_CFG_LEDMODE_PHY7_XI                    (9L<<8)
0902 #define BNX2_MISC_CFG_LEDMODE_PHY8_XI                    (10L<<8)
0903 #define BNX2_MISC_CFG_LEDMODE_PHY9_XI                    (11L<<8)
0904 #define BNX2_MISC_CFG_LEDMODE_MAC4_XI                    (12L<<8)
0905 #define BNX2_MISC_CFG_LEDMODE_PHY10_XI                   (13L<<8)
0906 #define BNX2_MISC_CFG_LEDMODE_PHY11_XI                   (14L<<8)
0907 #define BNX2_MISC_CFG_LEDMODE_UNUSED_XI                  (15L<<8)
0908 #define BNX2_MISC_CFG_PORT_SELECT_XI                     (1L<<13)
0909 #define BNX2_MISC_CFG_PARITY_MODE_XI                     (1L<<14)
0910 
0911 #define BNX2_MISC_ID                    0x00000808
0912 #define BNX2_MISC_ID_BOND_ID                             (0xfL<<0)
0913 #define BNX2_MISC_ID_BOND_ID_X                           (0L<<0)
0914 #define BNX2_MISC_ID_BOND_ID_C                           (3L<<0)
0915 #define BNX2_MISC_ID_BOND_ID_S                           (12L<<0)
0916 #define BNX2_MISC_ID_CHIP_METAL                          (0xffL<<4)
0917 #define BNX2_MISC_ID_CHIP_REV                            (0xfL<<12)
0918 #define BNX2_MISC_ID_CHIP_NUM                            (0xffffL<<16)
0919 
0920 #define BNX2_MISC_ENABLE_STATUS_BITS            0x0000080c
0921 #define BNX2_MISC_ENABLE_STATUS_BITS_TX_SCHEDULER_ENABLE         (1L<<0)
0922 #define BNX2_MISC_ENABLE_STATUS_BITS_TX_BD_READ_ENABLE   (1L<<1)
0923 #define BNX2_MISC_ENABLE_STATUS_BITS_TX_BD_CACHE_ENABLE  (1L<<2)
0924 #define BNX2_MISC_ENABLE_STATUS_BITS_TX_PROCESSOR_ENABLE         (1L<<3)
0925 #define BNX2_MISC_ENABLE_STATUS_BITS_TX_DMA_ENABLE       (1L<<4)
0926 #define BNX2_MISC_ENABLE_STATUS_BITS_TX_PATCHUP_ENABLE   (1L<<5)
0927 #define BNX2_MISC_ENABLE_STATUS_BITS_TX_PAYLOAD_Q_ENABLE         (1L<<6)
0928 #define BNX2_MISC_ENABLE_STATUS_BITS_TX_HEADER_Q_ENABLE  (1L<<7)
0929 #define BNX2_MISC_ENABLE_STATUS_BITS_TX_ASSEMBLER_ENABLE         (1L<<8)
0930 #define BNX2_MISC_ENABLE_STATUS_BITS_EMAC_ENABLE         (1L<<9)
0931 #define BNX2_MISC_ENABLE_STATUS_BITS_RX_PARSER_MAC_ENABLE        (1L<<10)
0932 #define BNX2_MISC_ENABLE_STATUS_BITS_RX_PARSER_CATCHUP_ENABLE    (1L<<11)
0933 #define BNX2_MISC_ENABLE_STATUS_BITS_RX_MBUF_ENABLE      (1L<<12)
0934 #define BNX2_MISC_ENABLE_STATUS_BITS_RX_LOOKUP_ENABLE    (1L<<13)
0935 #define BNX2_MISC_ENABLE_STATUS_BITS_RX_PROCESSOR_ENABLE         (1L<<14)
0936 #define BNX2_MISC_ENABLE_STATUS_BITS_RX_V2P_ENABLE       (1L<<15)
0937 #define BNX2_MISC_ENABLE_STATUS_BITS_RX_BD_CACHE_ENABLE  (1L<<16)
0938 #define BNX2_MISC_ENABLE_STATUS_BITS_RX_DMA_ENABLE       (1L<<17)
0939 #define BNX2_MISC_ENABLE_STATUS_BITS_COMPLETION_ENABLE   (1L<<18)
0940 #define BNX2_MISC_ENABLE_STATUS_BITS_HOST_COALESCE_ENABLE        (1L<<19)
0941 #define BNX2_MISC_ENABLE_STATUS_BITS_MAILBOX_QUEUE_ENABLE        (1L<<20)
0942 #define BNX2_MISC_ENABLE_STATUS_BITS_CONTEXT_ENABLE      (1L<<21)
0943 #define BNX2_MISC_ENABLE_STATUS_BITS_CMD_SCHEDULER_ENABLE        (1L<<22)
0944 #define BNX2_MISC_ENABLE_STATUS_BITS_CMD_PROCESSOR_ENABLE        (1L<<23)
0945 #define BNX2_MISC_ENABLE_STATUS_BITS_MGMT_PROCESSOR_ENABLE       (1L<<24)
0946 #define BNX2_MISC_ENABLE_STATUS_BITS_TIMER_ENABLE        (1L<<25)
0947 #define BNX2_MISC_ENABLE_STATUS_BITS_DMA_ENGINE_ENABLE   (1L<<26)
0948 #define BNX2_MISC_ENABLE_STATUS_BITS_UMP_ENABLE          (1L<<27)
0949 #define BNX2_MISC_ENABLE_STATUS_BITS_RV2P_CMD_SCHEDULER_ENABLE   (1L<<28)
0950 #define BNX2_MISC_ENABLE_STATUS_BITS_RSVD_FUTURE_ENABLE  (0x7L<<29)
0951 
0952 #define BNX2_MISC_ENABLE_SET_BITS           0x00000810
0953 #define BNX2_MISC_ENABLE_SET_BITS_TX_SCHEDULER_ENABLE    (1L<<0)
0954 #define BNX2_MISC_ENABLE_SET_BITS_TX_BD_READ_ENABLE      (1L<<1)
0955 #define BNX2_MISC_ENABLE_SET_BITS_TX_BD_CACHE_ENABLE     (1L<<2)
0956 #define BNX2_MISC_ENABLE_SET_BITS_TX_PROCESSOR_ENABLE    (1L<<3)
0957 #define BNX2_MISC_ENABLE_SET_BITS_TX_DMA_ENABLE          (1L<<4)
0958 #define BNX2_MISC_ENABLE_SET_BITS_TX_PATCHUP_ENABLE      (1L<<5)
0959 #define BNX2_MISC_ENABLE_SET_BITS_TX_PAYLOAD_Q_ENABLE    (1L<<6)
0960 #define BNX2_MISC_ENABLE_SET_BITS_TX_HEADER_Q_ENABLE     (1L<<7)
0961 #define BNX2_MISC_ENABLE_SET_BITS_TX_ASSEMBLER_ENABLE    (1L<<8)
0962 #define BNX2_MISC_ENABLE_SET_BITS_EMAC_ENABLE            (1L<<9)
0963 #define BNX2_MISC_ENABLE_SET_BITS_RX_PARSER_MAC_ENABLE   (1L<<10)
0964 #define BNX2_MISC_ENABLE_SET_BITS_RX_PARSER_CATCHUP_ENABLE       (1L<<11)
0965 #define BNX2_MISC_ENABLE_SET_BITS_RX_MBUF_ENABLE         (1L<<12)
0966 #define BNX2_MISC_ENABLE_SET_BITS_RX_LOOKUP_ENABLE       (1L<<13)
0967 #define BNX2_MISC_ENABLE_SET_BITS_RX_PROCESSOR_ENABLE    (1L<<14)
0968 #define BNX2_MISC_ENABLE_SET_BITS_RX_V2P_ENABLE          (1L<<15)
0969 #define BNX2_MISC_ENABLE_SET_BITS_RX_BD_CACHE_ENABLE     (1L<<16)
0970 #define BNX2_MISC_ENABLE_SET_BITS_RX_DMA_ENABLE          (1L<<17)
0971 #define BNX2_MISC_ENABLE_SET_BITS_COMPLETION_ENABLE      (1L<<18)
0972 #define BNX2_MISC_ENABLE_SET_BITS_HOST_COALESCE_ENABLE   (1L<<19)
0973 #define BNX2_MISC_ENABLE_SET_BITS_MAILBOX_QUEUE_ENABLE   (1L<<20)
0974 #define BNX2_MISC_ENABLE_SET_BITS_CONTEXT_ENABLE         (1L<<21)
0975 #define BNX2_MISC_ENABLE_SET_BITS_CMD_SCHEDULER_ENABLE   (1L<<22)
0976 #define BNX2_MISC_ENABLE_SET_BITS_CMD_PROCESSOR_ENABLE   (1L<<23)
0977 #define BNX2_MISC_ENABLE_SET_BITS_MGMT_PROCESSOR_ENABLE  (1L<<24)
0978 #define BNX2_MISC_ENABLE_SET_BITS_TIMER_ENABLE           (1L<<25)
0979 #define BNX2_MISC_ENABLE_SET_BITS_DMA_ENGINE_ENABLE      (1L<<26)
0980 #define BNX2_MISC_ENABLE_SET_BITS_UMP_ENABLE             (1L<<27)
0981 #define BNX2_MISC_ENABLE_SET_BITS_RV2P_CMD_SCHEDULER_ENABLE      (1L<<28)
0982 #define BNX2_MISC_ENABLE_SET_BITS_RSVD_FUTURE_ENABLE     (0x7L<<29)
0983 
0984 #define BNX2_MISC_ENABLE_CLR_BITS           0x00000814
0985 #define BNX2_MISC_ENABLE_CLR_BITS_TX_SCHEDULER_ENABLE    (1L<<0)
0986 #define BNX2_MISC_ENABLE_CLR_BITS_TX_BD_READ_ENABLE      (1L<<1)
0987 #define BNX2_MISC_ENABLE_CLR_BITS_TX_BD_CACHE_ENABLE     (1L<<2)
0988 #define BNX2_MISC_ENABLE_CLR_BITS_TX_PROCESSOR_ENABLE    (1L<<3)
0989 #define BNX2_MISC_ENABLE_CLR_BITS_TX_DMA_ENABLE          (1L<<4)
0990 #define BNX2_MISC_ENABLE_CLR_BITS_TX_PATCHUP_ENABLE      (1L<<5)
0991 #define BNX2_MISC_ENABLE_CLR_BITS_TX_PAYLOAD_Q_ENABLE    (1L<<6)
0992 #define BNX2_MISC_ENABLE_CLR_BITS_TX_HEADER_Q_ENABLE     (1L<<7)
0993 #define BNX2_MISC_ENABLE_CLR_BITS_TX_ASSEMBLER_ENABLE    (1L<<8)
0994 #define BNX2_MISC_ENABLE_CLR_BITS_EMAC_ENABLE            (1L<<9)
0995 #define BNX2_MISC_ENABLE_CLR_BITS_RX_PARSER_MAC_ENABLE   (1L<<10)
0996 #define BNX2_MISC_ENABLE_CLR_BITS_RX_PARSER_CATCHUP_ENABLE       (1L<<11)
0997 #define BNX2_MISC_ENABLE_CLR_BITS_RX_MBUF_ENABLE         (1L<<12)
0998 #define BNX2_MISC_ENABLE_CLR_BITS_RX_LOOKUP_ENABLE       (1L<<13)
0999 #define BNX2_MISC_ENABLE_CLR_BITS_RX_PROCESSOR_ENABLE    (1L<<14)
1000 #define BNX2_MISC_ENABLE_CLR_BITS_RX_V2P_ENABLE          (1L<<15)
1001 #define BNX2_MISC_ENABLE_CLR_BITS_RX_BD_CACHE_ENABLE     (1L<<16)
1002 #define BNX2_MISC_ENABLE_CLR_BITS_RX_DMA_ENABLE          (1L<<17)
1003 #define BNX2_MISC_ENABLE_CLR_BITS_COMPLETION_ENABLE      (1L<<18)
1004 #define BNX2_MISC_ENABLE_CLR_BITS_HOST_COALESCE_ENABLE   (1L<<19)
1005 #define BNX2_MISC_ENABLE_CLR_BITS_MAILBOX_QUEUE_ENABLE   (1L<<20)
1006 #define BNX2_MISC_ENABLE_CLR_BITS_CONTEXT_ENABLE         (1L<<21)
1007 #define BNX2_MISC_ENABLE_CLR_BITS_CMD_SCHEDULER_ENABLE   (1L<<22)
1008 #define BNX2_MISC_ENABLE_CLR_BITS_CMD_PROCESSOR_ENABLE   (1L<<23)
1009 #define BNX2_MISC_ENABLE_CLR_BITS_MGMT_PROCESSOR_ENABLE  (1L<<24)
1010 #define BNX2_MISC_ENABLE_CLR_BITS_TIMER_ENABLE           (1L<<25)
1011 #define BNX2_MISC_ENABLE_CLR_BITS_DMA_ENGINE_ENABLE      (1L<<26)
1012 #define BNX2_MISC_ENABLE_CLR_BITS_UMP_ENABLE             (1L<<27)
1013 #define BNX2_MISC_ENABLE_CLR_BITS_RV2P_CMD_SCHEDULER_ENABLE      (1L<<28)
1014 #define BNX2_MISC_ENABLE_CLR_BITS_RSVD_FUTURE_ENABLE     (0x7L<<29)
1015 
1016 #define BNX2_MISC_CLOCK_CONTROL_BITS            0x00000818
1017 #define BNX2_MISC_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET     (0xfL<<0)
1018 #define BNX2_MISC_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_32MHZ       (0L<<0)
1019 #define BNX2_MISC_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_38MHZ       (1L<<0)
1020 #define BNX2_MISC_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_48MHZ       (2L<<0)
1021 #define BNX2_MISC_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_55MHZ       (3L<<0)
1022 #define BNX2_MISC_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_66MHZ       (4L<<0)
1023 #define BNX2_MISC_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_80MHZ       (5L<<0)
1024 #define BNX2_MISC_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_95MHZ       (6L<<0)
1025 #define BNX2_MISC_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_133MHZ      (7L<<0)
1026 #define BNX2_MISC_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_LOW         (0xfL<<0)
1027 #define BNX2_MISC_CLOCK_CONTROL_BITS_CORE_CLK_DISABLE    (1L<<6)
1028 #define BNX2_MISC_CLOCK_CONTROL_BITS_CORE_CLK_ALT        (1L<<7)
1029 #define BNX2_MISC_CLOCK_CONTROL_BITS_CORE_CLK_ALT_SRC    (0x7L<<8)
1030 #define BNX2_MISC_CLOCK_CONTROL_BITS_CORE_CLK_ALT_SRC_UNDEF      (0L<<8)
1031 #define BNX2_MISC_CLOCK_CONTROL_BITS_CORE_CLK_ALT_SRC_12         (1L<<8)
1032 #define BNX2_MISC_CLOCK_CONTROL_BITS_CORE_CLK_ALT_SRC_6  (2L<<8)
1033 #define BNX2_MISC_CLOCK_CONTROL_BITS_CORE_CLK_ALT_SRC_62         (4L<<8)
1034 #define BNX2_MISC_CLOCK_CONTROL_BITS_RESERVED0_XI        (0x7L<<8)
1035 #define BNX2_MISC_CLOCK_CONTROL_BITS_MIN_POWER           (1L<<11)
1036 #define BNX2_MISC_CLOCK_CONTROL_BITS_CORE_CLK_PLL_SPEED  (0xfL<<12)
1037 #define BNX2_MISC_CLOCK_CONTROL_BITS_CORE_CLK_PLL_SPEED_100      (0L<<12)
1038 #define BNX2_MISC_CLOCK_CONTROL_BITS_CORE_CLK_PLL_SPEED_80       (1L<<12)
1039 #define BNX2_MISC_CLOCK_CONTROL_BITS_CORE_CLK_PLL_SPEED_50       (2L<<12)
1040 #define BNX2_MISC_CLOCK_CONTROL_BITS_CORE_CLK_PLL_SPEED_40       (4L<<12)
1041 #define BNX2_MISC_CLOCK_CONTROL_BITS_CORE_CLK_PLL_SPEED_25       (8L<<12)
1042 #define BNX2_MISC_CLOCK_CONTROL_BITS_RESERVED1_XI        (0xfL<<12)
1043 #define BNX2_MISC_CLOCK_CONTROL_BITS_CORE_CLK_PLL_STOP   (1L<<16)
1044 #define BNX2_MISC_CLOCK_CONTROL_BITS_RESERVED_17_TE      (1L<<17)
1045 #define BNX2_MISC_CLOCK_CONTROL_BITS_RESERVED_18_TE      (1L<<18)
1046 #define BNX2_MISC_CLOCK_CONTROL_BITS_RESERVED_19_TE      (1L<<19)
1047 #define BNX2_MISC_CLOCK_CONTROL_BITS_RESERVED_TE         (0xfffL<<20)
1048 #define BNX2_MISC_CLOCK_CONTROL_BITS_CORE_CLK_ALT_MGMT_XI        (1L<<17)
1049 #define BNX2_MISC_CLOCK_CONTROL_BITS_RESERVED2_XI        (0x3fL<<18)
1050 #define BNX2_MISC_CLOCK_CONTROL_BITS_CORE_CLK_PLL_VCO_XI         (0x7L<<24)
1051 #define BNX2_MISC_CLOCK_CONTROL_BITS_RESERVED3_XI        (1L<<27)
1052 #define BNX2_MISC_CLOCK_CONTROL_BITS_CORE_CLK_PLL_SPEED_XI       (0xfL<<28)
1053 
1054 #define BNX2_MISC_SPIO                  0x0000081c
1055 #define BNX2_MISC_SPIO_VALUE                             (0xffL<<0)
1056 #define BNX2_MISC_SPIO_SET                               (0xffL<<8)
1057 #define BNX2_MISC_SPIO_CLR                               (0xffL<<16)
1058 #define BNX2_MISC_SPIO_FLOAT                             (0xffL<<24)
1059 
1060 #define BNX2_MISC_SPIO_INT              0x00000820
1061 #define BNX2_MISC_SPIO_INT_INT_STATE_TE                  (0xfL<<0)
1062 #define BNX2_MISC_SPIO_INT_OLD_VALUE_TE                  (0xfL<<8)
1063 #define BNX2_MISC_SPIO_INT_OLD_SET_TE                    (0xfL<<16)
1064 #define BNX2_MISC_SPIO_INT_OLD_CLR_TE                    (0xfL<<24)
1065 #define BNX2_MISC_SPIO_INT_INT_STATE_XI                  (0xffL<<0)
1066 #define BNX2_MISC_SPIO_INT_OLD_VALUE_XI                  (0xffL<<8)
1067 #define BNX2_MISC_SPIO_INT_OLD_SET_XI                    (0xffL<<16)
1068 #define BNX2_MISC_SPIO_INT_OLD_CLR_XI                    (0xffL<<24)
1069 
1070 #define BNX2_MISC_CONFIG_LFSR               0x00000824
1071 #define BNX2_MISC_CONFIG_LFSR_DIV                        (0xffffL<<0)
1072 
1073 #define BNX2_MISC_LFSR_MASK_BITS            0x00000828
1074 #define BNX2_MISC_LFSR_MASK_BITS_TX_SCHEDULER_ENABLE     (1L<<0)
1075 #define BNX2_MISC_LFSR_MASK_BITS_TX_BD_READ_ENABLE       (1L<<1)
1076 #define BNX2_MISC_LFSR_MASK_BITS_TX_BD_CACHE_ENABLE      (1L<<2)
1077 #define BNX2_MISC_LFSR_MASK_BITS_TX_PROCESSOR_ENABLE     (1L<<3)
1078 #define BNX2_MISC_LFSR_MASK_BITS_TX_DMA_ENABLE           (1L<<4)
1079 #define BNX2_MISC_LFSR_MASK_BITS_TX_PATCHUP_ENABLE       (1L<<5)
1080 #define BNX2_MISC_LFSR_MASK_BITS_TX_PAYLOAD_Q_ENABLE     (1L<<6)
1081 #define BNX2_MISC_LFSR_MASK_BITS_TX_HEADER_Q_ENABLE      (1L<<7)
1082 #define BNX2_MISC_LFSR_MASK_BITS_TX_ASSEMBLER_ENABLE     (1L<<8)
1083 #define BNX2_MISC_LFSR_MASK_BITS_EMAC_ENABLE             (1L<<9)
1084 #define BNX2_MISC_LFSR_MASK_BITS_RX_PARSER_MAC_ENABLE    (1L<<10)
1085 #define BNX2_MISC_LFSR_MASK_BITS_RX_PARSER_CATCHUP_ENABLE        (1L<<11)
1086 #define BNX2_MISC_LFSR_MASK_BITS_RX_MBUF_ENABLE          (1L<<12)
1087 #define BNX2_MISC_LFSR_MASK_BITS_RX_LOOKUP_ENABLE        (1L<<13)
1088 #define BNX2_MISC_LFSR_MASK_BITS_RX_PROCESSOR_ENABLE     (1L<<14)
1089 #define BNX2_MISC_LFSR_MASK_BITS_RX_V2P_ENABLE           (1L<<15)
1090 #define BNX2_MISC_LFSR_MASK_BITS_RX_BD_CACHE_ENABLE      (1L<<16)
1091 #define BNX2_MISC_LFSR_MASK_BITS_RX_DMA_ENABLE           (1L<<17)
1092 #define BNX2_MISC_LFSR_MASK_BITS_COMPLETION_ENABLE       (1L<<18)
1093 #define BNX2_MISC_LFSR_MASK_BITS_HOST_COALESCE_ENABLE    (1L<<19)
1094 #define BNX2_MISC_LFSR_MASK_BITS_MAILBOX_QUEUE_ENABLE    (1L<<20)
1095 #define BNX2_MISC_LFSR_MASK_BITS_CONTEXT_ENABLE          (1L<<21)
1096 #define BNX2_MISC_LFSR_MASK_BITS_CMD_SCHEDULER_ENABLE    (1L<<22)
1097 #define BNX2_MISC_LFSR_MASK_BITS_CMD_PROCESSOR_ENABLE    (1L<<23)
1098 #define BNX2_MISC_LFSR_MASK_BITS_MGMT_PROCESSOR_ENABLE   (1L<<24)
1099 #define BNX2_MISC_LFSR_MASK_BITS_TIMER_ENABLE            (1L<<25)
1100 #define BNX2_MISC_LFSR_MASK_BITS_DMA_ENGINE_ENABLE       (1L<<26)
1101 #define BNX2_MISC_LFSR_MASK_BITS_UMP_ENABLE              (1L<<27)
1102 #define BNX2_MISC_LFSR_MASK_BITS_RV2P_CMD_SCHEDULER_ENABLE       (1L<<28)
1103 #define BNX2_MISC_LFSR_MASK_BITS_RSVD_FUTURE_ENABLE      (0x7L<<29)
1104 
1105 #define BNX2_MISC_ARB_REQ0              0x0000082c
1106 #define BNX2_MISC_ARB_REQ1              0x00000830
1107 #define BNX2_MISC_ARB_REQ2              0x00000834
1108 #define BNX2_MISC_ARB_REQ3              0x00000838
1109 #define BNX2_MISC_ARB_REQ4              0x0000083c
1110 #define BNX2_MISC_ARB_FREE0             0x00000840
1111 #define BNX2_MISC_ARB_FREE1             0x00000844
1112 #define BNX2_MISC_ARB_FREE2             0x00000848
1113 #define BNX2_MISC_ARB_FREE3             0x0000084c
1114 #define BNX2_MISC_ARB_FREE4             0x00000850
1115 #define BNX2_MISC_ARB_REQ_STATUS0           0x00000854
1116 #define BNX2_MISC_ARB_REQ_STATUS1           0x00000858
1117 #define BNX2_MISC_ARB_REQ_STATUS2           0x0000085c
1118 #define BNX2_MISC_ARB_REQ_STATUS3           0x00000860
1119 #define BNX2_MISC_ARB_REQ_STATUS4           0x00000864
1120 #define BNX2_MISC_ARB_GNT0              0x00000868
1121 #define BNX2_MISC_ARB_GNT0_0                             (0x7L<<0)
1122 #define BNX2_MISC_ARB_GNT0_1                             (0x7L<<4)
1123 #define BNX2_MISC_ARB_GNT0_2                             (0x7L<<8)
1124 #define BNX2_MISC_ARB_GNT0_3                             (0x7L<<12)
1125 #define BNX2_MISC_ARB_GNT0_4                             (0x7L<<16)
1126 #define BNX2_MISC_ARB_GNT0_5                             (0x7L<<20)
1127 #define BNX2_MISC_ARB_GNT0_6                             (0x7L<<24)
1128 #define BNX2_MISC_ARB_GNT0_7                             (0x7L<<28)
1129 
1130 #define BNX2_MISC_ARB_GNT1              0x0000086c
1131 #define BNX2_MISC_ARB_GNT1_8                             (0x7L<<0)
1132 #define BNX2_MISC_ARB_GNT1_9                             (0x7L<<4)
1133 #define BNX2_MISC_ARB_GNT1_10                            (0x7L<<8)
1134 #define BNX2_MISC_ARB_GNT1_11                            (0x7L<<12)
1135 #define BNX2_MISC_ARB_GNT1_12                            (0x7L<<16)
1136 #define BNX2_MISC_ARB_GNT1_13                            (0x7L<<20)
1137 #define BNX2_MISC_ARB_GNT1_14                            (0x7L<<24)
1138 #define BNX2_MISC_ARB_GNT1_15                            (0x7L<<28)
1139 
1140 #define BNX2_MISC_ARB_GNT2              0x00000870
1141 #define BNX2_MISC_ARB_GNT2_16                            (0x7L<<0)
1142 #define BNX2_MISC_ARB_GNT2_17                            (0x7L<<4)
1143 #define BNX2_MISC_ARB_GNT2_18                            (0x7L<<8)
1144 #define BNX2_MISC_ARB_GNT2_19                            (0x7L<<12)
1145 #define BNX2_MISC_ARB_GNT2_20                            (0x7L<<16)
1146 #define BNX2_MISC_ARB_GNT2_21                            (0x7L<<20)
1147 #define BNX2_MISC_ARB_GNT2_22                            (0x7L<<24)
1148 #define BNX2_MISC_ARB_GNT2_23                            (0x7L<<28)
1149 
1150 #define BNX2_MISC_ARB_GNT3              0x00000874
1151 #define BNX2_MISC_ARB_GNT3_24                            (0x7L<<0)
1152 #define BNX2_MISC_ARB_GNT3_25                            (0x7L<<4)
1153 #define BNX2_MISC_ARB_GNT3_26                            (0x7L<<8)
1154 #define BNX2_MISC_ARB_GNT3_27                            (0x7L<<12)
1155 #define BNX2_MISC_ARB_GNT3_28                            (0x7L<<16)
1156 #define BNX2_MISC_ARB_GNT3_29                            (0x7L<<20)
1157 #define BNX2_MISC_ARB_GNT3_30                            (0x7L<<24)
1158 #define BNX2_MISC_ARB_GNT3_31                            (0x7L<<28)
1159 
1160 #define BNX2_MISC_RESERVED1             0x00000878
1161 #define BNX2_MISC_RESERVED1_MISC_RESERVED1_VALUE         (0x3fL<<0)
1162 
1163 #define BNX2_MISC_RESERVED2             0x0000087c
1164 #define BNX2_MISC_RESERVED2_PCIE_DIS                     (1L<<0)
1165 #define BNX2_MISC_RESERVED2_LINK_IN_L23                  (1L<<1)
1166 
1167 #define BNX2_MISC_SM_ASF_CONTROL            0x00000880
1168 #define BNX2_MISC_SM_ASF_CONTROL_ASF_RST                 (1L<<0)
1169 #define BNX2_MISC_SM_ASF_CONTROL_TSC_EN                  (1L<<1)
1170 #define BNX2_MISC_SM_ASF_CONTROL_WG_TO                   (1L<<2)
1171 #define BNX2_MISC_SM_ASF_CONTROL_HB_TO                   (1L<<3)
1172 #define BNX2_MISC_SM_ASF_CONTROL_PA_TO                   (1L<<4)
1173 #define BNX2_MISC_SM_ASF_CONTROL_PL_TO                   (1L<<5)
1174 #define BNX2_MISC_SM_ASF_CONTROL_RT_TO                   (1L<<6)
1175 #define BNX2_MISC_SM_ASF_CONTROL_SMB_EVENT               (1L<<7)
1176 #define BNX2_MISC_SM_ASF_CONTROL_STRETCH_EN              (1L<<8)
1177 #define BNX2_MISC_SM_ASF_CONTROL_STRETCH_PULSE           (1L<<9)
1178 #define BNX2_MISC_SM_ASF_CONTROL_RES                     (0x3L<<10)
1179 #define BNX2_MISC_SM_ASF_CONTROL_SMB_EN                  (1L<<12)
1180 #define BNX2_MISC_SM_ASF_CONTROL_SMB_BB_EN               (1L<<13)
1181 #define BNX2_MISC_SM_ASF_CONTROL_SMB_NO_ADDR_FILT        (1L<<14)
1182 #define BNX2_MISC_SM_ASF_CONTROL_SMB_AUTOREAD            (1L<<15)
1183 #define BNX2_MISC_SM_ASF_CONTROL_NIC_SMB_ADDR1           (0x7fL<<16)
1184 #define BNX2_MISC_SM_ASF_CONTROL_NIC_SMB_ADDR2           (0x7fL<<23)
1185 #define BNX2_MISC_SM_ASF_CONTROL_EN_NIC_SMB_ADDR_0       (1L<<30)
1186 #define BNX2_MISC_SM_ASF_CONTROL_SMB_EARLY_ATTN          (1L<<31)
1187 
1188 #define BNX2_MISC_SMB_IN                0x00000884
1189 #define BNX2_MISC_SMB_IN_DAT_IN                          (0xffL<<0)
1190 #define BNX2_MISC_SMB_IN_RDY                             (1L<<8)
1191 #define BNX2_MISC_SMB_IN_DONE                            (1L<<9)
1192 #define BNX2_MISC_SMB_IN_FIRSTBYTE                       (1L<<10)
1193 #define BNX2_MISC_SMB_IN_STATUS                          (0x7L<<11)
1194 #define BNX2_MISC_SMB_IN_STATUS_OK                       (0x0L<<11)
1195 #define BNX2_MISC_SMB_IN_STATUS_PEC                      (0x1L<<11)
1196 #define BNX2_MISC_SMB_IN_STATUS_OFLOW                    (0x2L<<11)
1197 #define BNX2_MISC_SMB_IN_STATUS_STOP                     (0x3L<<11)
1198 #define BNX2_MISC_SMB_IN_STATUS_TIMEOUT                  (0x4L<<11)
1199 
1200 #define BNX2_MISC_SMB_OUT               0x00000888
1201 #define BNX2_MISC_SMB_OUT_DAT_OUT                        (0xffL<<0)
1202 #define BNX2_MISC_SMB_OUT_RDY                            (1L<<8)
1203 #define BNX2_MISC_SMB_OUT_START                          (1L<<9)
1204 #define BNX2_MISC_SMB_OUT_LAST                           (1L<<10)
1205 #define BNX2_MISC_SMB_OUT_ACC_TYPE                       (1L<<11)
1206 #define BNX2_MISC_SMB_OUT_ENB_PEC                        (1L<<12)
1207 #define BNX2_MISC_SMB_OUT_GET_RX_LEN                     (1L<<13)
1208 #define BNX2_MISC_SMB_OUT_SMB_READ_LEN                   (0x3fL<<14)
1209 #define BNX2_MISC_SMB_OUT_SMB_OUT_STATUS                 (0xfL<<20)
1210 #define BNX2_MISC_SMB_OUT_SMB_OUT_STATUS_OK              (0L<<20)
1211 #define BNX2_MISC_SMB_OUT_SMB_OUT_STATUS_FIRST_NACK      (1L<<20)
1212 #define BNX2_MISC_SMB_OUT_SMB_OUT_STATUS_UFLOW           (2L<<20)
1213 #define BNX2_MISC_SMB_OUT_SMB_OUT_STATUS_STOP            (3L<<20)
1214 #define BNX2_MISC_SMB_OUT_SMB_OUT_STATUS_TIMEOUT         (4L<<20)
1215 #define BNX2_MISC_SMB_OUT_SMB_OUT_STATUS_FIRST_LOST      (5L<<20)
1216 #define BNX2_MISC_SMB_OUT_SMB_OUT_STATUS_BADACK          (6L<<20)
1217 #define BNX2_MISC_SMB_OUT_SMB_OUT_STATUS_SUB_NACK        (9L<<20)
1218 #define BNX2_MISC_SMB_OUT_SMB_OUT_STATUS_SUB_LOST        (0xdL<<20)
1219 #define BNX2_MISC_SMB_OUT_SMB_OUT_SLAVEMODE              (1L<<24)
1220 #define BNX2_MISC_SMB_OUT_SMB_OUT_DAT_EN                 (1L<<25)
1221 #define BNX2_MISC_SMB_OUT_SMB_OUT_DAT_IN                 (1L<<26)
1222 #define BNX2_MISC_SMB_OUT_SMB_OUT_CLK_EN                 (1L<<27)
1223 #define BNX2_MISC_SMB_OUT_SMB_OUT_CLK_IN                 (1L<<28)
1224 
1225 #define BNX2_MISC_SMB_WATCHDOG              0x0000088c
1226 #define BNX2_MISC_SMB_WATCHDOG_WATCHDOG                  (0xffffL<<0)
1227 
1228 #define BNX2_MISC_SMB_HEARTBEAT             0x00000890
1229 #define BNX2_MISC_SMB_HEARTBEAT_HEARTBEAT                (0xffffL<<0)
1230 
1231 #define BNX2_MISC_SMB_POLL_ASF              0x00000894
1232 #define BNX2_MISC_SMB_POLL_ASF_POLL_ASF                  (0xffffL<<0)
1233 
1234 #define BNX2_MISC_SMB_POLL_LEGACY           0x00000898
1235 #define BNX2_MISC_SMB_POLL_LEGACY_POLL_LEGACY            (0xffffL<<0)
1236 
1237 #define BNX2_MISC_SMB_RETRAN                0x0000089c
1238 #define BNX2_MISC_SMB_RETRAN_RETRAN                      (0xffL<<0)
1239 
1240 #define BNX2_MISC_SMB_TIMESTAMP             0x000008a0
1241 #define BNX2_MISC_SMB_TIMESTAMP_TIMESTAMP                (0xffffffffL<<0)
1242 
1243 #define BNX2_MISC_PERR_ENA0             0x000008a4
1244 #define BNX2_MISC_PERR_ENA0_COM_MISC_CTXC                (1L<<0)
1245 #define BNX2_MISC_PERR_ENA0_COM_MISC_REGF                (1L<<1)
1246 #define BNX2_MISC_PERR_ENA0_COM_MISC_SCPAD               (1L<<2)
1247 #define BNX2_MISC_PERR_ENA0_CP_MISC_CTXC                 (1L<<3)
1248 #define BNX2_MISC_PERR_ENA0_CP_MISC_REGF                 (1L<<4)
1249 #define BNX2_MISC_PERR_ENA0_CP_MISC_SCPAD                (1L<<5)
1250 #define BNX2_MISC_PERR_ENA0_CS_MISC_TMEM                 (1L<<6)
1251 #define BNX2_MISC_PERR_ENA0_CTX_MISC_ACCM0               (1L<<7)
1252 #define BNX2_MISC_PERR_ENA0_CTX_MISC_ACCM1               (1L<<8)
1253 #define BNX2_MISC_PERR_ENA0_CTX_MISC_ACCM2               (1L<<9)
1254 #define BNX2_MISC_PERR_ENA0_CTX_MISC_ACCM3               (1L<<10)
1255 #define BNX2_MISC_PERR_ENA0_CTX_MISC_ACCM4               (1L<<11)
1256 #define BNX2_MISC_PERR_ENA0_CTX_MISC_ACCM5               (1L<<12)
1257 #define BNX2_MISC_PERR_ENA0_CTX_MISC_PGTBL               (1L<<13)
1258 #define BNX2_MISC_PERR_ENA0_DMAE_MISC_DR0                (1L<<14)
1259 #define BNX2_MISC_PERR_ENA0_DMAE_MISC_DR1                (1L<<15)
1260 #define BNX2_MISC_PERR_ENA0_DMAE_MISC_DR2                (1L<<16)
1261 #define BNX2_MISC_PERR_ENA0_DMAE_MISC_DR3                (1L<<17)
1262 #define BNX2_MISC_PERR_ENA0_DMAE_MISC_DR4                (1L<<18)
1263 #define BNX2_MISC_PERR_ENA0_DMAE_MISC_DW0                (1L<<19)
1264 #define BNX2_MISC_PERR_ENA0_DMAE_MISC_DW1                (1L<<20)
1265 #define BNX2_MISC_PERR_ENA0_DMAE_MISC_DW2                (1L<<21)
1266 #define BNX2_MISC_PERR_ENA0_HC_MISC_DMA                  (1L<<22)
1267 #define BNX2_MISC_PERR_ENA0_MCP_MISC_REGF                (1L<<23)
1268 #define BNX2_MISC_PERR_ENA0_MCP_MISC_SCPAD               (1L<<24)
1269 #define BNX2_MISC_PERR_ENA0_MQ_MISC_CTX                  (1L<<25)
1270 #define BNX2_MISC_PERR_ENA0_RBDC_MISC                    (1L<<26)
1271 #define BNX2_MISC_PERR_ENA0_RBUF_MISC_MB                 (1L<<27)
1272 #define BNX2_MISC_PERR_ENA0_RBUF_MISC_PTR                (1L<<28)
1273 #define BNX2_MISC_PERR_ENA0_RDE_MISC_RPC                 (1L<<29)
1274 #define BNX2_MISC_PERR_ENA0_RDE_MISC_RPM                 (1L<<30)
1275 #define BNX2_MISC_PERR_ENA0_RV2P_MISC_CB0REGS            (1L<<31)
1276 #define BNX2_MISC_PERR_ENA0_COM_DMAE_PERR_EN_XI          (1L<<0)
1277 #define BNX2_MISC_PERR_ENA0_CP_DMAE_PERR_EN_XI           (1L<<1)
1278 #define BNX2_MISC_PERR_ENA0_RPM_ACPIBEMEM_PERR_EN_XI     (1L<<2)
1279 #define BNX2_MISC_PERR_ENA0_CTX_USAGE_CNT_PERR_EN_XI     (1L<<3)
1280 #define BNX2_MISC_PERR_ENA0_CTX_PGTBL_PERR_EN_XI         (1L<<4)
1281 #define BNX2_MISC_PERR_ENA0_CTX_CACHE_PERR_EN_XI         (1L<<5)
1282 #define BNX2_MISC_PERR_ENA0_CTX_MIRROR_PERR_EN_XI        (1L<<6)
1283 #define BNX2_MISC_PERR_ENA0_COM_CTXC_PERR_EN_XI          (1L<<7)
1284 #define BNX2_MISC_PERR_ENA0_COM_SCPAD_PERR_EN_XI         (1L<<8)
1285 #define BNX2_MISC_PERR_ENA0_CP_CTXC_PERR_EN_XI           (1L<<9)
1286 #define BNX2_MISC_PERR_ENA0_CP_SCPAD_PERR_EN_XI          (1L<<10)
1287 #define BNX2_MISC_PERR_ENA0_RXP_RBUFC_PERR_EN_XI         (1L<<11)
1288 #define BNX2_MISC_PERR_ENA0_RXP_CTXC_PERR_EN_XI          (1L<<12)
1289 #define BNX2_MISC_PERR_ENA0_RXP_SCPAD_PERR_EN_XI         (1L<<13)
1290 #define BNX2_MISC_PERR_ENA0_TPAT_SCPAD_PERR_EN_XI        (1L<<14)
1291 #define BNX2_MISC_PERR_ENA0_TXP_CTXC_PERR_EN_XI          (1L<<15)
1292 #define BNX2_MISC_PERR_ENA0_TXP_SCPAD_PERR_EN_XI         (1L<<16)
1293 #define BNX2_MISC_PERR_ENA0_CS_TMEM_PERR_EN_XI           (1L<<17)
1294 #define BNX2_MISC_PERR_ENA0_MQ_CTX_PERR_EN_XI            (1L<<18)
1295 #define BNX2_MISC_PERR_ENA0_RPM_DFIFOMEM_PERR_EN_XI      (1L<<19)
1296 #define BNX2_MISC_PERR_ENA0_RPC_DFIFOMEM_PERR_EN_XI      (1L<<20)
1297 #define BNX2_MISC_PERR_ENA0_RBUF_PTRMEM_PERR_EN_XI       (1L<<21)
1298 #define BNX2_MISC_PERR_ENA0_RBUF_DATAMEM_PERR_EN_XI      (1L<<22)
1299 #define BNX2_MISC_PERR_ENA0_RV2P_P2IRAM_PERR_EN_XI       (1L<<23)
1300 #define BNX2_MISC_PERR_ENA0_RV2P_P1IRAM_PERR_EN_XI       (1L<<24)
1301 #define BNX2_MISC_PERR_ENA0_RV2P_CB1REGS_PERR_EN_XI      (1L<<25)
1302 #define BNX2_MISC_PERR_ENA0_RV2P_CB0REGS_PERR_EN_XI      (1L<<26)
1303 #define BNX2_MISC_PERR_ENA0_TPBUF_PERR_EN_XI             (1L<<27)
1304 #define BNX2_MISC_PERR_ENA0_THBUF_PERR_EN_XI             (1L<<28)
1305 #define BNX2_MISC_PERR_ENA0_TDMA_PERR_EN_XI              (1L<<29)
1306 #define BNX2_MISC_PERR_ENA0_TBDC_PERR_EN_XI              (1L<<30)
1307 #define BNX2_MISC_PERR_ENA0_TSCH_LR_PERR_EN_XI           (1L<<31)
1308 
1309 #define BNX2_MISC_PERR_ENA1             0x000008a8
1310 #define BNX2_MISC_PERR_ENA1_RV2P_MISC_CB1REGS            (1L<<0)
1311 #define BNX2_MISC_PERR_ENA1_RV2P_MISC_P1IRAM             (1L<<1)
1312 #define BNX2_MISC_PERR_ENA1_RV2P_MISC_P2IRAM             (1L<<2)
1313 #define BNX2_MISC_PERR_ENA1_RXP_MISC_CTXC                (1L<<3)
1314 #define BNX2_MISC_PERR_ENA1_RXP_MISC_REGF                (1L<<4)
1315 #define BNX2_MISC_PERR_ENA1_RXP_MISC_SCPAD               (1L<<5)
1316 #define BNX2_MISC_PERR_ENA1_RXP_MISC_RBUFC               (1L<<6)
1317 #define BNX2_MISC_PERR_ENA1_TBDC_MISC                    (1L<<7)
1318 #define BNX2_MISC_PERR_ENA1_TDMA_MISC                    (1L<<8)
1319 #define BNX2_MISC_PERR_ENA1_THBUF_MISC_MB0               (1L<<9)
1320 #define BNX2_MISC_PERR_ENA1_THBUF_MISC_MB1               (1L<<10)
1321 #define BNX2_MISC_PERR_ENA1_TPAT_MISC_REGF               (1L<<11)
1322 #define BNX2_MISC_PERR_ENA1_TPAT_MISC_SCPAD              (1L<<12)
1323 #define BNX2_MISC_PERR_ENA1_TPBUF_MISC_MB                (1L<<13)
1324 #define BNX2_MISC_PERR_ENA1_TSCH_MISC_LR                 (1L<<14)
1325 #define BNX2_MISC_PERR_ENA1_TXP_MISC_CTXC                (1L<<15)
1326 #define BNX2_MISC_PERR_ENA1_TXP_MISC_REGF                (1L<<16)
1327 #define BNX2_MISC_PERR_ENA1_TXP_MISC_SCPAD               (1L<<17)
1328 #define BNX2_MISC_PERR_ENA1_UMP_MISC_FIORX               (1L<<18)
1329 #define BNX2_MISC_PERR_ENA1_UMP_MISC_FIOTX               (1L<<19)
1330 #define BNX2_MISC_PERR_ENA1_UMP_MISC_RX                  (1L<<20)
1331 #define BNX2_MISC_PERR_ENA1_UMP_MISC_TX                  (1L<<21)
1332 #define BNX2_MISC_PERR_ENA1_RDMAQ_MISC                   (1L<<22)
1333 #define BNX2_MISC_PERR_ENA1_CSQ_MISC                     (1L<<23)
1334 #define BNX2_MISC_PERR_ENA1_CPQ_MISC                     (1L<<24)
1335 #define BNX2_MISC_PERR_ENA1_MCPQ_MISC                    (1L<<25)
1336 #define BNX2_MISC_PERR_ENA1_RV2PMQ_MISC                  (1L<<26)
1337 #define BNX2_MISC_PERR_ENA1_RV2PPQ_MISC                  (1L<<27)
1338 #define BNX2_MISC_PERR_ENA1_RV2PTQ_MISC                  (1L<<28)
1339 #define BNX2_MISC_PERR_ENA1_RXPQ_MISC                    (1L<<29)
1340 #define BNX2_MISC_PERR_ENA1_RXPCQ_MISC                   (1L<<30)
1341 #define BNX2_MISC_PERR_ENA1_RLUPQ_MISC                   (1L<<31)
1342 #define BNX2_MISC_PERR_ENA1_RBDC_PERR_EN_XI              (1L<<0)
1343 #define BNX2_MISC_PERR_ENA1_RDMA_DFIFO_PERR_EN_XI        (1L<<2)
1344 #define BNX2_MISC_PERR_ENA1_HC_STATS_PERR_EN_XI          (1L<<3)
1345 #define BNX2_MISC_PERR_ENA1_HC_MSIX_PERR_EN_XI           (1L<<4)
1346 #define BNX2_MISC_PERR_ENA1_HC_PRODUCSTB_PERR_EN_XI      (1L<<5)
1347 #define BNX2_MISC_PERR_ENA1_HC_CONSUMSTB_PERR_EN_XI      (1L<<6)
1348 #define BNX2_MISC_PERR_ENA1_TPATQ_PERR_EN_XI             (1L<<7)
1349 #define BNX2_MISC_PERR_ENA1_MCPQ_PERR_EN_XI              (1L<<8)
1350 #define BNX2_MISC_PERR_ENA1_TDMAQ_PERR_EN_XI             (1L<<9)
1351 #define BNX2_MISC_PERR_ENA1_TXPQ_PERR_EN_XI              (1L<<10)
1352 #define BNX2_MISC_PERR_ENA1_COMTQ_PERR_EN_XI             (1L<<11)
1353 #define BNX2_MISC_PERR_ENA1_COMQ_PERR_EN_XI              (1L<<12)
1354 #define BNX2_MISC_PERR_ENA1_RLUPQ_PERR_EN_XI             (1L<<13)
1355 #define BNX2_MISC_PERR_ENA1_RXPQ_PERR_EN_XI              (1L<<14)
1356 #define BNX2_MISC_PERR_ENA1_RV2PPQ_PERR_EN_XI            (1L<<15)
1357 #define BNX2_MISC_PERR_ENA1_RDMAQ_PERR_EN_XI             (1L<<16)
1358 #define BNX2_MISC_PERR_ENA1_TASQ_PERR_EN_XI              (1L<<17)
1359 #define BNX2_MISC_PERR_ENA1_TBDRQ_PERR_EN_XI             (1L<<18)
1360 #define BNX2_MISC_PERR_ENA1_TSCHQ_PERR_EN_XI             (1L<<19)
1361 #define BNX2_MISC_PERR_ENA1_COMXQ_PERR_EN_XI             (1L<<20)
1362 #define BNX2_MISC_PERR_ENA1_RXPCQ_PERR_EN_XI             (1L<<21)
1363 #define BNX2_MISC_PERR_ENA1_RV2PTQ_PERR_EN_XI            (1L<<22)
1364 #define BNX2_MISC_PERR_ENA1_RV2PMQ_PERR_EN_XI            (1L<<23)
1365 #define BNX2_MISC_PERR_ENA1_CPQ_PERR_EN_XI               (1L<<24)
1366 #define BNX2_MISC_PERR_ENA1_CSQ_PERR_EN_XI               (1L<<25)
1367 #define BNX2_MISC_PERR_ENA1_RLUP_CID_PERR_EN_XI          (1L<<26)
1368 #define BNX2_MISC_PERR_ENA1_RV2PCS_TMEM_PERR_EN_XI       (1L<<27)
1369 #define BNX2_MISC_PERR_ENA1_RV2PCSQ_PERR_EN_XI           (1L<<28)
1370 #define BNX2_MISC_PERR_ENA1_MQ_IDX_PERR_EN_XI            (1L<<29)
1371 
1372 #define BNX2_MISC_PERR_ENA2             0x000008ac
1373 #define BNX2_MISC_PERR_ENA2_COMQ_MISC                    (1L<<0)
1374 #define BNX2_MISC_PERR_ENA2_COMXQ_MISC                   (1L<<1)
1375 #define BNX2_MISC_PERR_ENA2_COMTQ_MISC                   (1L<<2)
1376 #define BNX2_MISC_PERR_ENA2_TSCHQ_MISC                   (1L<<3)
1377 #define BNX2_MISC_PERR_ENA2_TBDRQ_MISC                   (1L<<4)
1378 #define BNX2_MISC_PERR_ENA2_TXPQ_MISC                    (1L<<5)
1379 #define BNX2_MISC_PERR_ENA2_TDMAQ_MISC                   (1L<<6)
1380 #define BNX2_MISC_PERR_ENA2_TPATQ_MISC                   (1L<<7)
1381 #define BNX2_MISC_PERR_ENA2_TASQ_MISC                    (1L<<8)
1382 #define BNX2_MISC_PERR_ENA2_TGT_FIFO_PERR_EN_XI          (1L<<0)
1383 #define BNX2_MISC_PERR_ENA2_UMP_TX_PERR_EN_XI            (1L<<1)
1384 #define BNX2_MISC_PERR_ENA2_UMP_RX_PERR_EN_XI            (1L<<2)
1385 #define BNX2_MISC_PERR_ENA2_MCP_ROM_PERR_EN_XI           (1L<<3)
1386 #define BNX2_MISC_PERR_ENA2_MCP_SCPAD_PERR_EN_XI         (1L<<4)
1387 #define BNX2_MISC_PERR_ENA2_HB_MEM_PERR_EN_XI            (1L<<5)
1388 #define BNX2_MISC_PERR_ENA2_PCIE_REPLAY_PERR_EN_XI       (1L<<6)
1389 
1390 #define BNX2_MISC_DEBUG_VECTOR_SEL          0x000008b0
1391 #define BNX2_MISC_DEBUG_VECTOR_SEL_0                     (0xfffL<<0)
1392 #define BNX2_MISC_DEBUG_VECTOR_SEL_1                     (0xfffL<<12)
1393 #define BNX2_MISC_DEBUG_VECTOR_SEL_1_XI                  (0xfffL<<15)
1394 
1395 #define BNX2_MISC_VREG_CONTROL              0x000008b4
1396 #define BNX2_MISC_VREG_CONTROL_1_2                       (0xfL<<0)
1397 #define BNX2_MISC_VREG_CONTROL_1_0_MAIN_XI               (0xfL<<0)
1398 #define BNX2_MISC_VREG_CONTROL_1_0_MAIN_PLUS14_XI        (0L<<0)
1399 #define BNX2_MISC_VREG_CONTROL_1_0_MAIN_PLUS12_XI        (1L<<0)
1400 #define BNX2_MISC_VREG_CONTROL_1_0_MAIN_PLUS10_XI        (2L<<0)
1401 #define BNX2_MISC_VREG_CONTROL_1_0_MAIN_PLUS8_XI         (3L<<0)
1402 #define BNX2_MISC_VREG_CONTROL_1_0_MAIN_PLUS6_XI         (4L<<0)
1403 #define BNX2_MISC_VREG_CONTROL_1_0_MAIN_PLUS4_XI         (5L<<0)
1404 #define BNX2_MISC_VREG_CONTROL_1_0_MAIN_PLUS2_XI         (6L<<0)
1405 #define BNX2_MISC_VREG_CONTROL_1_0_MAIN_NOM_XI           (7L<<0)
1406 #define BNX2_MISC_VREG_CONTROL_1_0_MAIN_MINUS2_XI        (8L<<0)
1407 #define BNX2_MISC_VREG_CONTROL_1_0_MAIN_MINUS4_XI        (9L<<0)
1408 #define BNX2_MISC_VREG_CONTROL_1_0_MAIN_MINUS6_XI        (10L<<0)
1409 #define BNX2_MISC_VREG_CONTROL_1_0_MAIN_MINUS8_XI        (11L<<0)
1410 #define BNX2_MISC_VREG_CONTROL_1_0_MAIN_MINUS10_XI       (12L<<0)
1411 #define BNX2_MISC_VREG_CONTROL_1_0_MAIN_MINUS12_XI       (13L<<0)
1412 #define BNX2_MISC_VREG_CONTROL_1_0_MAIN_MINUS14_XI       (14L<<0)
1413 #define BNX2_MISC_VREG_CONTROL_1_0_MAIN_MINUS16_XI       (15L<<0)
1414 #define BNX2_MISC_VREG_CONTROL_2_5                       (0xfL<<4)
1415 #define BNX2_MISC_VREG_CONTROL_2_5_PLUS14                (0L<<4)
1416 #define BNX2_MISC_VREG_CONTROL_2_5_PLUS12                (1L<<4)
1417 #define BNX2_MISC_VREG_CONTROL_2_5_PLUS10                (2L<<4)
1418 #define BNX2_MISC_VREG_CONTROL_2_5_PLUS8                 (3L<<4)
1419 #define BNX2_MISC_VREG_CONTROL_2_5_PLUS6                 (4L<<4)
1420 #define BNX2_MISC_VREG_CONTROL_2_5_PLUS4                 (5L<<4)
1421 #define BNX2_MISC_VREG_CONTROL_2_5_PLUS2                 (6L<<4)
1422 #define BNX2_MISC_VREG_CONTROL_2_5_NOM                   (7L<<4)
1423 #define BNX2_MISC_VREG_CONTROL_2_5_MINUS2                (8L<<4)
1424 #define BNX2_MISC_VREG_CONTROL_2_5_MINUS4                (9L<<4)
1425 #define BNX2_MISC_VREG_CONTROL_2_5_MINUS6                (10L<<4)
1426 #define BNX2_MISC_VREG_CONTROL_2_5_MINUS8                (11L<<4)
1427 #define BNX2_MISC_VREG_CONTROL_2_5_MINUS10               (12L<<4)
1428 #define BNX2_MISC_VREG_CONTROL_2_5_MINUS12               (13L<<4)
1429 #define BNX2_MISC_VREG_CONTROL_2_5_MINUS14               (14L<<4)
1430 #define BNX2_MISC_VREG_CONTROL_2_5_MINUS16               (15L<<4)
1431 #define BNX2_MISC_VREG_CONTROL_1_0_MGMT                  (0xfL<<8)
1432 #define BNX2_MISC_VREG_CONTROL_1_0_MGMT_PLUS14           (0L<<8)
1433 #define BNX2_MISC_VREG_CONTROL_1_0_MGMT_PLUS12           (1L<<8)
1434 #define BNX2_MISC_VREG_CONTROL_1_0_MGMT_PLUS10           (2L<<8)
1435 #define BNX2_MISC_VREG_CONTROL_1_0_MGMT_PLUS8            (3L<<8)
1436 #define BNX2_MISC_VREG_CONTROL_1_0_MGMT_PLUS6            (4L<<8)
1437 #define BNX2_MISC_VREG_CONTROL_1_0_MGMT_PLUS4            (5L<<8)
1438 #define BNX2_MISC_VREG_CONTROL_1_0_MGMT_PLUS2            (6L<<8)
1439 #define BNX2_MISC_VREG_CONTROL_1_0_MGMT_NOM              (7L<<8)
1440 #define BNX2_MISC_VREG_CONTROL_1_0_MGMT_MINUS2           (8L<<8)
1441 #define BNX2_MISC_VREG_CONTROL_1_0_MGMT_MINUS4           (9L<<8)
1442 #define BNX2_MISC_VREG_CONTROL_1_0_MGMT_MINUS6           (10L<<8)
1443 #define BNX2_MISC_VREG_CONTROL_1_0_MGMT_MINUS8           (11L<<8)
1444 #define BNX2_MISC_VREG_CONTROL_1_0_MGMT_MINUS10          (12L<<8)
1445 #define BNX2_MISC_VREG_CONTROL_1_0_MGMT_MINUS12          (13L<<8)
1446 #define BNX2_MISC_VREG_CONTROL_1_0_MGMT_MINUS14          (14L<<8)
1447 #define BNX2_MISC_VREG_CONTROL_1_0_MGMT_MINUS16          (15L<<8)
1448 
1449 #define BNX2_MISC_FINAL_CLK_CTL_VAL         0x000008b8
1450 #define BNX2_MISC_FINAL_CLK_CTL_VAL_MISC_FINAL_CLK_CTL_VAL       (0x3ffffffL<<6)
1451 
1452 #define BNX2_MISC_GP_HW_CTL0                0x000008bc
1453 #define BNX2_MISC_GP_HW_CTL0_TX_DRIVE                    (1L<<0)
1454 #define BNX2_MISC_GP_HW_CTL0_RMII_MODE                   (1L<<1)
1455 #define BNX2_MISC_GP_HW_CTL0_RMII_CRSDV_SEL              (1L<<2)
1456 #define BNX2_MISC_GP_HW_CTL0_RVMII_MODE                  (1L<<3)
1457 #define BNX2_MISC_GP_HW_CTL0_FLASH_SAMP_SCLK_NEGEDGE_TE  (1L<<4)
1458 #define BNX2_MISC_GP_HW_CTL0_HIDDEN_REVISION_ID_TE       (1L<<5)
1459 #define BNX2_MISC_GP_HW_CTL0_HC_CNTL_TMOUT_CTR_RST_TE    (1L<<6)
1460 #define BNX2_MISC_GP_HW_CTL0_RESERVED1_XI                (0x7L<<4)
1461 #define BNX2_MISC_GP_HW_CTL0_ENA_CORE_RST_ON_MAIN_PWR_GOING_AWAY         (1L<<7)
1462 #define BNX2_MISC_GP_HW_CTL0_ENA_SEL_VAUX_B_IN_L2_TE     (1L<<8)
1463 #define BNX2_MISC_GP_HW_CTL0_GRC_BNK_FREE_FIX_TE         (1L<<9)
1464 #define BNX2_MISC_GP_HW_CTL0_LED_ACT_SEL_TE              (1L<<10)
1465 #define BNX2_MISC_GP_HW_CTL0_RESERVED2_XI                (0x7L<<8)
1466 #define BNX2_MISC_GP_HW_CTL0_UP1_DEF0                    (1L<<11)
1467 #define BNX2_MISC_GP_HW_CTL0_FIBER_MODE_DIS_DEF          (1L<<12)
1468 #define BNX2_MISC_GP_HW_CTL0_FORCE2500_DEF               (1L<<13)
1469 #define BNX2_MISC_GP_HW_CTL0_AUTODETECT_DIS_DEF          (1L<<14)
1470 #define BNX2_MISC_GP_HW_CTL0_PARALLEL_DETECT_DEF         (1L<<15)
1471 #define BNX2_MISC_GP_HW_CTL0_OSCCTRL_DAI                 (0xfL<<16)
1472 #define BNX2_MISC_GP_HW_CTL0_OSCCTRL_DAI_3MA             (0L<<16)
1473 #define BNX2_MISC_GP_HW_CTL0_OSCCTRL_DAI_2P5MA           (1L<<16)
1474 #define BNX2_MISC_GP_HW_CTL0_OSCCTRL_DAI_2P0MA           (3L<<16)
1475 #define BNX2_MISC_GP_HW_CTL0_OSCCTRL_DAI_1P5MA           (5L<<16)
1476 #define BNX2_MISC_GP_HW_CTL0_OSCCTRL_DAI_1P0MA           (7L<<16)
1477 #define BNX2_MISC_GP_HW_CTL0_OSCCTRL_DAI_PWRDN           (15L<<16)
1478 #define BNX2_MISC_GP_HW_CTL0_OSCCTRL_PRE2DIS             (1L<<20)
1479 #define BNX2_MISC_GP_HW_CTL0_OSCCTRL_PRE1DIS             (1L<<21)
1480 #define BNX2_MISC_GP_HW_CTL0_OSCCTRL_CTAT                (0x3L<<22)
1481 #define BNX2_MISC_GP_HW_CTL0_OSCCTRL_CTAT_M6P            (0L<<22)
1482 #define BNX2_MISC_GP_HW_CTL0_OSCCTRL_CTAT_M0P            (1L<<22)
1483 #define BNX2_MISC_GP_HW_CTL0_OSCCTRL_CTAT_P0P            (2L<<22)
1484 #define BNX2_MISC_GP_HW_CTL0_OSCCTRL_CTAT_P6P            (3L<<22)
1485 #define BNX2_MISC_GP_HW_CTL0_OSCCTRL_PTAT                (0x3L<<24)
1486 #define BNX2_MISC_GP_HW_CTL0_OSCCTRL_PTAT_M6P            (0L<<24)
1487 #define BNX2_MISC_GP_HW_CTL0_OSCCTRL_PTAT_M0P            (1L<<24)
1488 #define BNX2_MISC_GP_HW_CTL0_OSCCTRL_PTAT_P0P            (2L<<24)
1489 #define BNX2_MISC_GP_HW_CTL0_OSCCTRL_PTAT_P6P            (3L<<24)
1490 #define BNX2_MISC_GP_HW_CTL0_OSCCTRL_IAMP_ADJ            (0x3L<<26)
1491 #define BNX2_MISC_GP_HW_CTL0_OSCCTRL_IAMP_ADJ_240UA      (0L<<26)
1492 #define BNX2_MISC_GP_HW_CTL0_OSCCTRL_IAMP_ADJ_160UA      (1L<<26)
1493 #define BNX2_MISC_GP_HW_CTL0_OSCCTRL_IAMP_ADJ_400UA      (2L<<26)
1494 #define BNX2_MISC_GP_HW_CTL0_OSCCTRL_IAMP_ADJ_320UA      (3L<<26)
1495 #define BNX2_MISC_GP_HW_CTL0_OSCCTRL_ICBUF_ADJ           (0x3L<<28)
1496 #define BNX2_MISC_GP_HW_CTL0_OSCCTRL_ICBUF_ADJ_240UA     (0L<<28)
1497 #define BNX2_MISC_GP_HW_CTL0_OSCCTRL_ICBUF_ADJ_160UA     (1L<<28)
1498 #define BNX2_MISC_GP_HW_CTL0_OSCCTRL_ICBUF_ADJ_400UA     (2L<<28)
1499 #define BNX2_MISC_GP_HW_CTL0_OSCCTRL_ICBUF_ADJ_320UA     (3L<<28)
1500 #define BNX2_MISC_GP_HW_CTL0_OSCCTRL_XTAL_ADJ            (0x3L<<30)
1501 #define BNX2_MISC_GP_HW_CTL0_OSCCTRL_XTAL_ADJ_1P57       (0L<<30)
1502 #define BNX2_MISC_GP_HW_CTL0_OSCCTRL_XTAL_ADJ_1P45       (1L<<30)
1503 #define BNX2_MISC_GP_HW_CTL0_OSCCTRL_XTAL_ADJ_1P62       (2L<<30)
1504 #define BNX2_MISC_GP_HW_CTL0_OSCCTRL_XTAL_ADJ_1P66       (3L<<30)
1505 
1506 #define BNX2_MISC_GP_HW_CTL1                0x000008c0
1507 #define BNX2_MISC_GP_HW_CTL1_1_ATTN_BTN_PRSNT_TE         (1L<<0)
1508 #define BNX2_MISC_GP_HW_CTL1_1_ATTN_IND_PRSNT_TE         (1L<<1)
1509 #define BNX2_MISC_GP_HW_CTL1_1_PWR_IND_PRSNT_TE          (1L<<2)
1510 #define BNX2_MISC_GP_HW_CTL1_0_PCIE_LOOPBACK_TE          (1L<<3)
1511 #define BNX2_MISC_GP_HW_CTL1_RESERVED_SOFT_XI            (0xffffL<<0)
1512 #define BNX2_MISC_GP_HW_CTL1_RESERVED_HARD_XI            (0xffffL<<16)
1513 
1514 #define BNX2_MISC_NEW_HW_CTL                0x000008c4
1515 #define BNX2_MISC_NEW_HW_CTL_MAIN_POR_BYPASS             (1L<<0)
1516 #define BNX2_MISC_NEW_HW_CTL_RINGOSC_ENABLE              (1L<<1)
1517 #define BNX2_MISC_NEW_HW_CTL_RINGOSC_SEL0                (1L<<2)
1518 #define BNX2_MISC_NEW_HW_CTL_RINGOSC_SEL1                (1L<<3)
1519 #define BNX2_MISC_NEW_HW_CTL_RESERVED_SHARED             (0xfffL<<4)
1520 #define BNX2_MISC_NEW_HW_CTL_RESERVED_SPLIT              (0xffffL<<16)
1521 
1522 #define BNX2_MISC_NEW_CORE_CTL              0x000008c8
1523 #define BNX2_MISC_NEW_CORE_CTL_LINK_HOLDOFF_SUCCESS      (1L<<0)
1524 #define BNX2_MISC_NEW_CORE_CTL_LINK_HOLDOFF_REQ          (1L<<1)
1525 #define BNX2_MISC_NEW_CORE_CTL_DMA_ENABLE                (1L<<16)
1526 #define BNX2_MISC_NEW_CORE_CTL_RESERVED_CMN              (0x3fffL<<2)
1527 #define BNX2_MISC_NEW_CORE_CTL_RESERVED_TC               (0xffffL<<16)
1528 
1529 #define BNX2_MISC_ECO_HW_CTL                0x000008cc
1530 #define BNX2_MISC_ECO_HW_CTL_LARGE_GRC_TMOUT_EN          (1L<<0)
1531 #define BNX2_MISC_ECO_HW_CTL_RESERVED_SOFT               (0x7fffL<<1)
1532 #define BNX2_MISC_ECO_HW_CTL_RESERVED_HARD               (0xffffL<<16)
1533 
1534 #define BNX2_MISC_ECO_CORE_CTL              0x000008d0
1535 #define BNX2_MISC_ECO_CORE_CTL_RESERVED_SOFT             (0xffffL<<0)
1536 #define BNX2_MISC_ECO_CORE_CTL_RESERVED_HARD             (0xffffL<<16)
1537 
1538 #define BNX2_MISC_PPIO                  0x000008d4
1539 #define BNX2_MISC_PPIO_VALUE                             (0xfL<<0)
1540 #define BNX2_MISC_PPIO_SET                               (0xfL<<8)
1541 #define BNX2_MISC_PPIO_CLR                               (0xfL<<16)
1542 #define BNX2_MISC_PPIO_FLOAT                             (0xfL<<24)
1543 
1544 #define BNX2_MISC_PPIO_INT              0x000008d8
1545 #define BNX2_MISC_PPIO_INT_INT_STATE                     (0xfL<<0)
1546 #define BNX2_MISC_PPIO_INT_OLD_VALUE                     (0xfL<<8)
1547 #define BNX2_MISC_PPIO_INT_OLD_SET                       (0xfL<<16)
1548 #define BNX2_MISC_PPIO_INT_OLD_CLR                       (0xfL<<24)
1549 
1550 #define BNX2_MISC_RESET_NUMS                0x000008dc
1551 #define BNX2_MISC_RESET_NUMS_NUM_HARD_RESETS             (0x7L<<0)
1552 #define BNX2_MISC_RESET_NUMS_NUM_PCIE_RESETS             (0x7L<<4)
1553 #define BNX2_MISC_RESET_NUMS_NUM_PERSTB_RESETS           (0x7L<<8)
1554 #define BNX2_MISC_RESET_NUMS_NUM_CMN_RESETS              (0x7L<<12)
1555 #define BNX2_MISC_RESET_NUMS_NUM_PORT_RESETS             (0x7L<<16)
1556 
1557 #define BNX2_MISC_CS16_ERR              0x000008e0
1558 #define BNX2_MISC_CS16_ERR_ENA_PCI                       (1L<<0)
1559 #define BNX2_MISC_CS16_ERR_ENA_RDMA                      (1L<<1)
1560 #define BNX2_MISC_CS16_ERR_ENA_TDMA                      (1L<<2)
1561 #define BNX2_MISC_CS16_ERR_ENA_EMAC                      (1L<<3)
1562 #define BNX2_MISC_CS16_ERR_ENA_CTX                       (1L<<4)
1563 #define BNX2_MISC_CS16_ERR_ENA_TBDR                      (1L<<5)
1564 #define BNX2_MISC_CS16_ERR_ENA_RBDC                      (1L<<6)
1565 #define BNX2_MISC_CS16_ERR_ENA_COM                       (1L<<7)
1566 #define BNX2_MISC_CS16_ERR_ENA_CP                        (1L<<8)
1567 #define BNX2_MISC_CS16_ERR_STA_PCI                       (1L<<16)
1568 #define BNX2_MISC_CS16_ERR_STA_RDMA                      (1L<<17)
1569 #define BNX2_MISC_CS16_ERR_STA_TDMA                      (1L<<18)
1570 #define BNX2_MISC_CS16_ERR_STA_EMAC                      (1L<<19)
1571 #define BNX2_MISC_CS16_ERR_STA_CTX                       (1L<<20)
1572 #define BNX2_MISC_CS16_ERR_STA_TBDR                      (1L<<21)
1573 #define BNX2_MISC_CS16_ERR_STA_RBDC                      (1L<<22)
1574 #define BNX2_MISC_CS16_ERR_STA_COM                       (1L<<23)
1575 #define BNX2_MISC_CS16_ERR_STA_CP                        (1L<<24)
1576 
1577 #define BNX2_MISC_SPIO_EVENT                0x000008e4
1578 #define BNX2_MISC_SPIO_EVENT_ENABLE                      (0xffL<<0)
1579 
1580 #define BNX2_MISC_PPIO_EVENT                0x000008e8
1581 #define BNX2_MISC_PPIO_EVENT_ENABLE                      (0xfL<<0)
1582 
1583 #define BNX2_MISC_DUAL_MEDIA_CTRL           0x000008ec
1584 #define BNX2_MISC_DUAL_MEDIA_CTRL_BOND_ID                (0xffL<<0)
1585 #define BNX2_MISC_DUAL_MEDIA_CTRL_BOND_ID_X              (0L<<0)
1586 #define BNX2_MISC_DUAL_MEDIA_CTRL_BOND_ID_C              (3L<<0)
1587 #define BNX2_MISC_DUAL_MEDIA_CTRL_BOND_ID_S              (12L<<0)
1588 #define BNX2_MISC_DUAL_MEDIA_CTRL_PHY_CTRL_STRAP         (0x7L<<8)
1589 #define BNX2_MISC_DUAL_MEDIA_CTRL_PORT_SWAP_PIN          (1L<<11)
1590 #define BNX2_MISC_DUAL_MEDIA_CTRL_SERDES1_SIGDET         (1L<<12)
1591 #define BNX2_MISC_DUAL_MEDIA_CTRL_SERDES0_SIGDET         (1L<<13)
1592 #define BNX2_MISC_DUAL_MEDIA_CTRL_PHY1_SIGDET            (1L<<14)
1593 #define BNX2_MISC_DUAL_MEDIA_CTRL_PHY0_SIGDET            (1L<<15)
1594 #define BNX2_MISC_DUAL_MEDIA_CTRL_LCPLL_RST              (1L<<16)
1595 #define BNX2_MISC_DUAL_MEDIA_CTRL_SERDES1_RST            (1L<<17)
1596 #define BNX2_MISC_DUAL_MEDIA_CTRL_SERDES0_RST            (1L<<18)
1597 #define BNX2_MISC_DUAL_MEDIA_CTRL_PHY1_RST               (1L<<19)
1598 #define BNX2_MISC_DUAL_MEDIA_CTRL_PHY0_RST               (1L<<20)
1599 #define BNX2_MISC_DUAL_MEDIA_CTRL_PHY_CTRL               (0x7L<<21)
1600 #define BNX2_MISC_DUAL_MEDIA_CTRL_PORT_SWAP              (1L<<24)
1601 #define BNX2_MISC_DUAL_MEDIA_CTRL_STRAP_OVERRIDE         (1L<<25)
1602 #define BNX2_MISC_DUAL_MEDIA_CTRL_PHY_SERDES_IDDQ        (0xfL<<26)
1603 #define BNX2_MISC_DUAL_MEDIA_CTRL_PHY_SERDES_IDDQ_SER1_IDDQ      (1L<<26)
1604 #define BNX2_MISC_DUAL_MEDIA_CTRL_PHY_SERDES_IDDQ_SER0_IDDQ      (2L<<26)
1605 #define BNX2_MISC_DUAL_MEDIA_CTRL_PHY_SERDES_IDDQ_PHY1_IDDQ      (4L<<26)
1606 #define BNX2_MISC_DUAL_MEDIA_CTRL_PHY_SERDES_IDDQ_PHY0_IDDQ      (8L<<26)
1607 
1608 #define BNX2_MISC_OTP_CMD1              0x000008f0
1609 #define BNX2_MISC_OTP_CMD1_FMODE                         (0x7L<<0)
1610 #define BNX2_MISC_OTP_CMD1_FMODE_IDLE                    (0L<<0)
1611 #define BNX2_MISC_OTP_CMD1_FMODE_WRITE                   (1L<<0)
1612 #define BNX2_MISC_OTP_CMD1_FMODE_INIT                    (2L<<0)
1613 #define BNX2_MISC_OTP_CMD1_FMODE_SET                     (3L<<0)
1614 #define BNX2_MISC_OTP_CMD1_FMODE_RST                     (4L<<0)
1615 #define BNX2_MISC_OTP_CMD1_FMODE_VERIFY                  (5L<<0)
1616 #define BNX2_MISC_OTP_CMD1_FMODE_RESERVED0               (6L<<0)
1617 #define BNX2_MISC_OTP_CMD1_FMODE_RESERVED1               (7L<<0)
1618 #define BNX2_MISC_OTP_CMD1_USEPINS                       (1L<<8)
1619 #define BNX2_MISC_OTP_CMD1_PROGSEL                       (1L<<9)
1620 #define BNX2_MISC_OTP_CMD1_PROGSTART                     (1L<<10)
1621 #define BNX2_MISC_OTP_CMD1_PCOUNT                        (0x7L<<16)
1622 #define BNX2_MISC_OTP_CMD1_PBYP                          (1L<<19)
1623 #define BNX2_MISC_OTP_CMD1_VSEL                          (0xfL<<20)
1624 #define BNX2_MISC_OTP_CMD1_TM                            (0x7L<<27)
1625 #define BNX2_MISC_OTP_CMD1_SADBYP                        (1L<<30)
1626 #define BNX2_MISC_OTP_CMD1_DEBUG                         (1L<<31)
1627 
1628 #define BNX2_MISC_OTP_CMD2              0x000008f4
1629 #define BNX2_MISC_OTP_CMD2_OTP_ROM_ADDR                  (0x3ffL<<0)
1630 #define BNX2_MISC_OTP_CMD2_DOSEL                         (0x7fL<<16)
1631 #define BNX2_MISC_OTP_CMD2_DOSEL_0                       (0L<<16)
1632 #define BNX2_MISC_OTP_CMD2_DOSEL_1                       (1L<<16)
1633 #define BNX2_MISC_OTP_CMD2_DOSEL_127                     (127L<<16)
1634 
1635 #define BNX2_MISC_OTP_STATUS                0x000008f8
1636 #define BNX2_MISC_OTP_STATUS_DATA                        (0xffL<<0)
1637 #define BNX2_MISC_OTP_STATUS_VALID                       (1L<<8)
1638 #define BNX2_MISC_OTP_STATUS_BUSY                        (1L<<9)
1639 #define BNX2_MISC_OTP_STATUS_BUSYSM                      (1L<<10)
1640 #define BNX2_MISC_OTP_STATUS_DONE                        (1L<<11)
1641 
1642 #define BNX2_MISC_OTP_SHIFT1_CMD            0x000008fc
1643 #define BNX2_MISC_OTP_SHIFT1_CMD_RESET_MODE_N            (1L<<0)
1644 #define BNX2_MISC_OTP_SHIFT1_CMD_SHIFT_DONE              (1L<<1)
1645 #define BNX2_MISC_OTP_SHIFT1_CMD_SHIFT_START             (1L<<2)
1646 #define BNX2_MISC_OTP_SHIFT1_CMD_LOAD_DATA               (1L<<3)
1647 #define BNX2_MISC_OTP_SHIFT1_CMD_SHIFT_SELECT            (0x1fL<<8)
1648 
1649 #define BNX2_MISC_OTP_SHIFT1_DATA           0x00000900
1650 #define BNX2_MISC_OTP_SHIFT2_CMD            0x00000904
1651 #define BNX2_MISC_OTP_SHIFT2_CMD_RESET_MODE_N            (1L<<0)
1652 #define BNX2_MISC_OTP_SHIFT2_CMD_SHIFT_DONE              (1L<<1)
1653 #define BNX2_MISC_OTP_SHIFT2_CMD_SHIFT_START             (1L<<2)
1654 #define BNX2_MISC_OTP_SHIFT2_CMD_LOAD_DATA               (1L<<3)
1655 #define BNX2_MISC_OTP_SHIFT2_CMD_SHIFT_SELECT            (0x1fL<<8)
1656 
1657 #define BNX2_MISC_OTP_SHIFT2_DATA           0x00000908
1658 #define BNX2_MISC_BIST_CS0              0x0000090c
1659 #define BNX2_MISC_BIST_CS0_MBIST_EN                      (1L<<0)
1660 #define BNX2_MISC_BIST_CS0_BIST_SETUP                    (0x3L<<1)
1661 #define BNX2_MISC_BIST_CS0_MBIST_ASYNC_RESET             (1L<<3)
1662 #define BNX2_MISC_BIST_CS0_MBIST_DONE                    (1L<<8)
1663 #define BNX2_MISC_BIST_CS0_MBIST_GO                      (1L<<9)
1664 #define BNX2_MISC_BIST_CS0_BIST_OVERRIDE                 (1L<<31)
1665 
1666 #define BNX2_MISC_BIST_MEMSTATUS0           0x00000910
1667 #define BNX2_MISC_BIST_CS1              0x00000914
1668 #define BNX2_MISC_BIST_CS1_MBIST_EN                      (1L<<0)
1669 #define BNX2_MISC_BIST_CS1_BIST_SETUP                    (0x3L<<1)
1670 #define BNX2_MISC_BIST_CS1_MBIST_ASYNC_RESET             (1L<<3)
1671 #define BNX2_MISC_BIST_CS1_MBIST_DONE                    (1L<<8)
1672 #define BNX2_MISC_BIST_CS1_MBIST_GO                      (1L<<9)
1673 
1674 #define BNX2_MISC_BIST_MEMSTATUS1           0x00000918
1675 #define BNX2_MISC_BIST_CS2              0x0000091c
1676 #define BNX2_MISC_BIST_CS2_MBIST_EN                      (1L<<0)
1677 #define BNX2_MISC_BIST_CS2_BIST_SETUP                    (0x3L<<1)
1678 #define BNX2_MISC_BIST_CS2_MBIST_ASYNC_RESET             (1L<<3)
1679 #define BNX2_MISC_BIST_CS2_MBIST_DONE                    (1L<<8)
1680 #define BNX2_MISC_BIST_CS2_MBIST_GO                      (1L<<9)
1681 
1682 #define BNX2_MISC_BIST_MEMSTATUS2           0x00000920
1683 #define BNX2_MISC_BIST_CS3              0x00000924
1684 #define BNX2_MISC_BIST_CS3_MBIST_EN                      (1L<<0)
1685 #define BNX2_MISC_BIST_CS3_BIST_SETUP                    (0x3L<<1)
1686 #define BNX2_MISC_BIST_CS3_MBIST_ASYNC_RESET             (1L<<3)
1687 #define BNX2_MISC_BIST_CS3_MBIST_DONE                    (1L<<8)
1688 #define BNX2_MISC_BIST_CS3_MBIST_GO                      (1L<<9)
1689 
1690 #define BNX2_MISC_BIST_MEMSTATUS3           0x00000928
1691 #define BNX2_MISC_BIST_CS4              0x0000092c
1692 #define BNX2_MISC_BIST_CS4_MBIST_EN                      (1L<<0)
1693 #define BNX2_MISC_BIST_CS4_BIST_SETUP                    (0x3L<<1)
1694 #define BNX2_MISC_BIST_CS4_MBIST_ASYNC_RESET             (1L<<3)
1695 #define BNX2_MISC_BIST_CS4_MBIST_DONE                    (1L<<8)
1696 #define BNX2_MISC_BIST_CS4_MBIST_GO                      (1L<<9)
1697 
1698 #define BNX2_MISC_BIST_MEMSTATUS4           0x00000930
1699 #define BNX2_MISC_BIST_CS5              0x00000934
1700 #define BNX2_MISC_BIST_CS5_MBIST_EN                      (1L<<0)
1701 #define BNX2_MISC_BIST_CS5_BIST_SETUP                    (0x3L<<1)
1702 #define BNX2_MISC_BIST_CS5_MBIST_ASYNC_RESET             (1L<<3)
1703 #define BNX2_MISC_BIST_CS5_MBIST_DONE                    (1L<<8)
1704 #define BNX2_MISC_BIST_CS5_MBIST_GO                      (1L<<9)
1705 
1706 #define BNX2_MISC_BIST_MEMSTATUS5           0x00000938
1707 #define BNX2_MISC_MEM_TM0               0x0000093c
1708 #define BNX2_MISC_MEM_TM0_PCIE_REPLAY_TM                 (0xfL<<0)
1709 #define BNX2_MISC_MEM_TM0_MCP_SCPAD                      (0xfL<<8)
1710 #define BNX2_MISC_MEM_TM0_UMP_TM                         (0xffL<<16)
1711 #define BNX2_MISC_MEM_TM0_HB_MEM_TM                      (0xfL<<24)
1712 
1713 #define BNX2_MISC_USPLL_CTRL                0x00000940
1714 #define BNX2_MISC_USPLL_CTRL_PH_DET_DIS                  (1L<<0)
1715 #define BNX2_MISC_USPLL_CTRL_FREQ_DET_DIS                (1L<<1)
1716 #define BNX2_MISC_USPLL_CTRL_LCPX                        (0x3fL<<2)
1717 #define BNX2_MISC_USPLL_CTRL_RX                          (0x3L<<8)
1718 #define BNX2_MISC_USPLL_CTRL_VC_EN                       (1L<<10)
1719 #define BNX2_MISC_USPLL_CTRL_VCO_MG                      (0x3L<<11)
1720 #define BNX2_MISC_USPLL_CTRL_KVCO_XF                     (0x7L<<13)
1721 #define BNX2_MISC_USPLL_CTRL_KVCO_XS                     (0x7L<<16)
1722 #define BNX2_MISC_USPLL_CTRL_TESTD_EN                    (1L<<19)
1723 #define BNX2_MISC_USPLL_CTRL_TESTD_SEL                   (0x7L<<20)
1724 #define BNX2_MISC_USPLL_CTRL_TESTA_EN                    (1L<<23)
1725 #define BNX2_MISC_USPLL_CTRL_TESTA_SEL                   (0x3L<<24)
1726 #define BNX2_MISC_USPLL_CTRL_ATTEN_FREF                  (1L<<26)
1727 #define BNX2_MISC_USPLL_CTRL_DIGITAL_RST                 (1L<<27)
1728 #define BNX2_MISC_USPLL_CTRL_ANALOG_RST                  (1L<<28)
1729 #define BNX2_MISC_USPLL_CTRL_LOCK                        (1L<<29)
1730 
1731 #define BNX2_MISC_PERR_STATUS0              0x00000944
1732 #define BNX2_MISC_PERR_STATUS0_COM_DMAE_PERR             (1L<<0)
1733 #define BNX2_MISC_PERR_STATUS0_CP_DMAE_PERR              (1L<<1)
1734 #define BNX2_MISC_PERR_STATUS0_RPM_ACPIBEMEM_PERR        (1L<<2)
1735 #define BNX2_MISC_PERR_STATUS0_CTX_USAGE_CNT_PERR        (1L<<3)
1736 #define BNX2_MISC_PERR_STATUS0_CTX_PGTBL_PERR            (1L<<4)
1737 #define BNX2_MISC_PERR_STATUS0_CTX_CACHE_PERR            (1L<<5)
1738 #define BNX2_MISC_PERR_STATUS0_CTX_MIRROR_PERR           (1L<<6)
1739 #define BNX2_MISC_PERR_STATUS0_COM_CTXC_PERR             (1L<<7)
1740 #define BNX2_MISC_PERR_STATUS0_COM_SCPAD_PERR            (1L<<8)
1741 #define BNX2_MISC_PERR_STATUS0_CP_CTXC_PERR              (1L<<9)
1742 #define BNX2_MISC_PERR_STATUS0_CP_SCPAD_PERR             (1L<<10)
1743 #define BNX2_MISC_PERR_STATUS0_RXP_RBUFC_PERR            (1L<<11)
1744 #define BNX2_MISC_PERR_STATUS0_RXP_CTXC_PERR             (1L<<12)
1745 #define BNX2_MISC_PERR_STATUS0_RXP_SCPAD_PERR            (1L<<13)
1746 #define BNX2_MISC_PERR_STATUS0_TPAT_SCPAD_PERR           (1L<<14)
1747 #define BNX2_MISC_PERR_STATUS0_TXP_CTXC_PERR             (1L<<15)
1748 #define BNX2_MISC_PERR_STATUS0_TXP_SCPAD_PERR            (1L<<16)
1749 #define BNX2_MISC_PERR_STATUS0_CS_TMEM_PERR              (1L<<17)
1750 #define BNX2_MISC_PERR_STATUS0_MQ_CTX_PERR               (1L<<18)
1751 #define BNX2_MISC_PERR_STATUS0_RPM_DFIFOMEM_PERR         (1L<<19)
1752 #define BNX2_MISC_PERR_STATUS0_RPC_DFIFOMEM_PERR         (1L<<20)
1753 #define BNX2_MISC_PERR_STATUS0_RBUF_PTRMEM_PERR          (1L<<21)
1754 #define BNX2_MISC_PERR_STATUS0_RBUF_DATAMEM_PERR         (1L<<22)
1755 #define BNX2_MISC_PERR_STATUS0_RV2P_P2IRAM_PERR          (1L<<23)
1756 #define BNX2_MISC_PERR_STATUS0_RV2P_P1IRAM_PERR          (1L<<24)
1757 #define BNX2_MISC_PERR_STATUS0_RV2P_CB1REGS_PERR         (1L<<25)
1758 #define BNX2_MISC_PERR_STATUS0_RV2P_CB0REGS_PERR         (1L<<26)
1759 #define BNX2_MISC_PERR_STATUS0_TPBUF_PERR                (1L<<27)
1760 #define BNX2_MISC_PERR_STATUS0_THBUF_PERR                (1L<<28)
1761 #define BNX2_MISC_PERR_STATUS0_TDMA_PERR                 (1L<<29)
1762 #define BNX2_MISC_PERR_STATUS0_TBDC_PERR                 (1L<<30)
1763 #define BNX2_MISC_PERR_STATUS0_TSCH_LR_PERR              (1L<<31)
1764 
1765 #define BNX2_MISC_PERR_STATUS1              0x00000948
1766 #define BNX2_MISC_PERR_STATUS1_RBDC_PERR                 (1L<<0)
1767 #define BNX2_MISC_PERR_STATUS1_RDMA_DFIFO_PERR           (1L<<2)
1768 #define BNX2_MISC_PERR_STATUS1_HC_STATS_PERR             (1L<<3)
1769 #define BNX2_MISC_PERR_STATUS1_HC_MSIX_PERR              (1L<<4)
1770 #define BNX2_MISC_PERR_STATUS1_HC_PRODUCSTB_PERR         (1L<<5)
1771 #define BNX2_MISC_PERR_STATUS1_HC_CONSUMSTB_PERR         (1L<<6)
1772 #define BNX2_MISC_PERR_STATUS1_TPATQ_PERR                (1L<<7)
1773 #define BNX2_MISC_PERR_STATUS1_MCPQ_PERR                 (1L<<8)
1774 #define BNX2_MISC_PERR_STATUS1_TDMAQ_PERR                (1L<<9)
1775 #define BNX2_MISC_PERR_STATUS1_TXPQ_PERR                 (1L<<10)
1776 #define BNX2_MISC_PERR_STATUS1_COMTQ_PERR                (1L<<11)
1777 #define BNX2_MISC_PERR_STATUS1_COMQ_PERR                 (1L<<12)
1778 #define BNX2_MISC_PERR_STATUS1_RLUPQ_PERR                (1L<<13)
1779 #define BNX2_MISC_PERR_STATUS1_RXPQ_PERR                 (1L<<14)
1780 #define BNX2_MISC_PERR_STATUS1_RV2PPQ_PERR               (1L<<15)
1781 #define BNX2_MISC_PERR_STATUS1_RDMAQ_PERR                (1L<<16)
1782 #define BNX2_MISC_PERR_STATUS1_TASQ_PERR                 (1L<<17)
1783 #define BNX2_MISC_PERR_STATUS1_TBDRQ_PERR                (1L<<18)
1784 #define BNX2_MISC_PERR_STATUS1_TSCHQ_PERR                (1L<<19)
1785 #define BNX2_MISC_PERR_STATUS1_COMXQ_PERR                (1L<<20)
1786 #define BNX2_MISC_PERR_STATUS1_RXPCQ_PERR                (1L<<21)
1787 #define BNX2_MISC_PERR_STATUS1_RV2PTQ_PERR               (1L<<22)
1788 #define BNX2_MISC_PERR_STATUS1_RV2PMQ_PERR               (1L<<23)
1789 #define BNX2_MISC_PERR_STATUS1_CPQ_PERR                  (1L<<24)
1790 #define BNX2_MISC_PERR_STATUS1_CSQ_PERR                  (1L<<25)
1791 #define BNX2_MISC_PERR_STATUS1_RLUP_CID_PERR             (1L<<26)
1792 #define BNX2_MISC_PERR_STATUS1_RV2PCS_TMEM_PERR          (1L<<27)
1793 #define BNX2_MISC_PERR_STATUS1_RV2PCSQ_PERR              (1L<<28)
1794 #define BNX2_MISC_PERR_STATUS1_MQ_IDX_PERR               (1L<<29)
1795 
1796 #define BNX2_MISC_PERR_STATUS2              0x0000094c
1797 #define BNX2_MISC_PERR_STATUS2_TGT_FIFO_PERR             (1L<<0)
1798 #define BNX2_MISC_PERR_STATUS2_UMP_TX_PERR               (1L<<1)
1799 #define BNX2_MISC_PERR_STATUS2_UMP_RX_PERR               (1L<<2)
1800 #define BNX2_MISC_PERR_STATUS2_MCP_ROM_PERR              (1L<<3)
1801 #define BNX2_MISC_PERR_STATUS2_MCP_SCPAD_PERR            (1L<<4)
1802 #define BNX2_MISC_PERR_STATUS2_HB_MEM_PERR               (1L<<5)
1803 #define BNX2_MISC_PERR_STATUS2_PCIE_REPLAY_PERR          (1L<<6)
1804 
1805 #define BNX2_MISC_LCPLL_CTRL0               0x00000950
1806 #define BNX2_MISC_LCPLL_CTRL0_OAC                        (0x7L<<0)
1807 #define BNX2_MISC_LCPLL_CTRL0_OAC_NEGTWENTY              (0L<<0)
1808 #define BNX2_MISC_LCPLL_CTRL0_OAC_ZERO                   (1L<<0)
1809 #define BNX2_MISC_LCPLL_CTRL0_OAC_TWENTY                 (3L<<0)
1810 #define BNX2_MISC_LCPLL_CTRL0_OAC_FORTY                  (7L<<0)
1811 #define BNX2_MISC_LCPLL_CTRL0_ICP_CTRL                   (0x7L<<3)
1812 #define BNX2_MISC_LCPLL_CTRL0_ICP_CTRL_360               (0L<<3)
1813 #define BNX2_MISC_LCPLL_CTRL0_ICP_CTRL_480               (1L<<3)
1814 #define BNX2_MISC_LCPLL_CTRL0_ICP_CTRL_600               (3L<<3)
1815 #define BNX2_MISC_LCPLL_CTRL0_ICP_CTRL_720               (7L<<3)
1816 #define BNX2_MISC_LCPLL_CTRL0_BIAS_CTRL                  (0x3L<<6)
1817 #define BNX2_MISC_LCPLL_CTRL0_PLL_OBSERVE                (0x7L<<8)
1818 #define BNX2_MISC_LCPLL_CTRL0_VTH_CTRL                   (0x3L<<11)
1819 #define BNX2_MISC_LCPLL_CTRL0_VTH_CTRL_0                 (0L<<11)
1820 #define BNX2_MISC_LCPLL_CTRL0_VTH_CTRL_1                 (1L<<11)
1821 #define BNX2_MISC_LCPLL_CTRL0_VTH_CTRL_2                 (2L<<11)
1822 #define BNX2_MISC_LCPLL_CTRL0_PLLSEQSTART                (1L<<13)
1823 #define BNX2_MISC_LCPLL_CTRL0_RESERVED                   (1L<<14)
1824 #define BNX2_MISC_LCPLL_CTRL0_CAPRETRY_EN                (1L<<15)
1825 #define BNX2_MISC_LCPLL_CTRL0_FREQMONITOR_EN             (1L<<16)
1826 #define BNX2_MISC_LCPLL_CTRL0_FREQDETRESTART_EN          (1L<<17)
1827 #define BNX2_MISC_LCPLL_CTRL0_FREQDETRETRY_EN            (1L<<18)
1828 #define BNX2_MISC_LCPLL_CTRL0_PLLFORCEFDONE_EN           (1L<<19)
1829 #define BNX2_MISC_LCPLL_CTRL0_PLLFORCEFDONE              (1L<<20)
1830 #define BNX2_MISC_LCPLL_CTRL0_PLLFORCEFPASS              (1L<<21)
1831 #define BNX2_MISC_LCPLL_CTRL0_PLLFORCECAPDONE_EN         (1L<<22)
1832 #define BNX2_MISC_LCPLL_CTRL0_PLLFORCECAPDONE            (1L<<23)
1833 #define BNX2_MISC_LCPLL_CTRL0_PLLFORCECAPPASS_EN         (1L<<24)
1834 #define BNX2_MISC_LCPLL_CTRL0_PLLFORCECAPPASS            (1L<<25)
1835 #define BNX2_MISC_LCPLL_CTRL0_CAPRESTART                 (1L<<26)
1836 #define BNX2_MISC_LCPLL_CTRL0_CAPSELECTM_EN              (1L<<27)
1837 
1838 #define BNX2_MISC_LCPLL_CTRL1               0x00000954
1839 #define BNX2_MISC_LCPLL_CTRL1_CAPSELECTM                 (0x1fL<<0)
1840 #define BNX2_MISC_LCPLL_CTRL1_CAPFORCESLOWDOWN_EN        (1L<<5)
1841 #define BNX2_MISC_LCPLL_CTRL1_CAPFORCESLOWDOWN           (1L<<6)
1842 #define BNX2_MISC_LCPLL_CTRL1_SLOWDN_XOR                 (1L<<7)
1843 
1844 #define BNX2_MISC_LCPLL_STATUS              0x00000958
1845 #define BNX2_MISC_LCPLL_STATUS_FREQDONE_SM               (1L<<0)
1846 #define BNX2_MISC_LCPLL_STATUS_FREQPASS_SM               (1L<<1)
1847 #define BNX2_MISC_LCPLL_STATUS_PLLSEQDONE                (1L<<2)
1848 #define BNX2_MISC_LCPLL_STATUS_PLLSEQPASS                (1L<<3)
1849 #define BNX2_MISC_LCPLL_STATUS_PLLSTATE                  (0x7L<<4)
1850 #define BNX2_MISC_LCPLL_STATUS_CAPSTATE                  (0x7L<<7)
1851 #define BNX2_MISC_LCPLL_STATUS_CAPSELECT                 (0x1fL<<10)
1852 #define BNX2_MISC_LCPLL_STATUS_SLOWDN_INDICATOR          (1L<<15)
1853 #define BNX2_MISC_LCPLL_STATUS_SLOWDN_INDICATOR_0        (0L<<15)
1854 #define BNX2_MISC_LCPLL_STATUS_SLOWDN_INDICATOR_1        (1L<<15)
1855 
1856 #define BNX2_MISC_OSCFUNDS_CTRL             0x0000095c
1857 #define BNX2_MISC_OSCFUNDS_CTRL_FREQ_MON                 (1L<<5)
1858 #define BNX2_MISC_OSCFUNDS_CTRL_FREQ_MON_OFF             (0L<<5)
1859 #define BNX2_MISC_OSCFUNDS_CTRL_FREQ_MON_ON              (1L<<5)
1860 #define BNX2_MISC_OSCFUNDS_CTRL_XTAL_ADJCM               (0x3L<<6)
1861 #define BNX2_MISC_OSCFUNDS_CTRL_XTAL_ADJCM_0             (0L<<6)
1862 #define BNX2_MISC_OSCFUNDS_CTRL_XTAL_ADJCM_1             (1L<<6)
1863 #define BNX2_MISC_OSCFUNDS_CTRL_XTAL_ADJCM_2             (2L<<6)
1864 #define BNX2_MISC_OSCFUNDS_CTRL_XTAL_ADJCM_3             (3L<<6)
1865 #define BNX2_MISC_OSCFUNDS_CTRL_ICBUF_ADJ                (0x3L<<8)
1866 #define BNX2_MISC_OSCFUNDS_CTRL_ICBUF_ADJ_0              (0L<<8)
1867 #define BNX2_MISC_OSCFUNDS_CTRL_ICBUF_ADJ_1              (1L<<8)
1868 #define BNX2_MISC_OSCFUNDS_CTRL_ICBUF_ADJ_2              (2L<<8)
1869 #define BNX2_MISC_OSCFUNDS_CTRL_ICBUF_ADJ_3              (3L<<8)
1870 #define BNX2_MISC_OSCFUNDS_CTRL_IAMP_ADJ                 (0x3L<<10)
1871 #define BNX2_MISC_OSCFUNDS_CTRL_IAMP_ADJ_0               (0L<<10)
1872 #define BNX2_MISC_OSCFUNDS_CTRL_IAMP_ADJ_1               (1L<<10)
1873 #define BNX2_MISC_OSCFUNDS_CTRL_IAMP_ADJ_2               (2L<<10)
1874 #define BNX2_MISC_OSCFUNDS_CTRL_IAMP_ADJ_3               (3L<<10)
1875 
1876 
1877 /*
1878  *  nvm_reg definition
1879  *  offset: 0x6400
1880  */
1881 #define BNX2_NVM_COMMAND                0x00006400
1882 #define BNX2_NVM_COMMAND_RST                             (1L<<0)
1883 #define BNX2_NVM_COMMAND_DONE                            (1L<<3)
1884 #define BNX2_NVM_COMMAND_DOIT                            (1L<<4)
1885 #define BNX2_NVM_COMMAND_WR                              (1L<<5)
1886 #define BNX2_NVM_COMMAND_ERASE                           (1L<<6)
1887 #define BNX2_NVM_COMMAND_FIRST                           (1L<<7)
1888 #define BNX2_NVM_COMMAND_LAST                            (1L<<8)
1889 #define BNX2_NVM_COMMAND_WREN                            (1L<<16)
1890 #define BNX2_NVM_COMMAND_WRDI                            (1L<<17)
1891 #define BNX2_NVM_COMMAND_EWSR                            (1L<<18)
1892 #define BNX2_NVM_COMMAND_WRSR                            (1L<<19)
1893 #define BNX2_NVM_COMMAND_RD_ID                           (1L<<20)
1894 #define BNX2_NVM_COMMAND_RD_STATUS                       (1L<<21)
1895 #define BNX2_NVM_COMMAND_MODE_256                        (1L<<22)
1896 
1897 #define BNX2_NVM_STATUS                 0x00006404
1898 #define BNX2_NVM_STATUS_PI_FSM_STATE                     (0xfL<<0)
1899 #define BNX2_NVM_STATUS_EE_FSM_STATE                     (0xfL<<4)
1900 #define BNX2_NVM_STATUS_EQ_FSM_STATE                     (0xfL<<8)
1901 #define BNX2_NVM_STATUS_SPI_FSM_STATE_XI                 (0x1fL<<0)
1902 #define BNX2_NVM_STATUS_SPI_FSM_STATE_SPI_IDLE_XI        (0L<<0)
1903 #define BNX2_NVM_STATUS_SPI_FSM_STATE_SPI_CMD0_XI        (1L<<0)
1904 #define BNX2_NVM_STATUS_SPI_FSM_STATE_SPI_CMD1_XI        (2L<<0)
1905 #define BNX2_NVM_STATUS_SPI_FSM_STATE_SPI_CMD_FINISH0_XI         (3L<<0)
1906 #define BNX2_NVM_STATUS_SPI_FSM_STATE_SPI_CMD_FINISH1_XI         (4L<<0)
1907 #define BNX2_NVM_STATUS_SPI_FSM_STATE_SPI_ADDR0_XI       (5L<<0)
1908 #define BNX2_NVM_STATUS_SPI_FSM_STATE_SPI_WRITE_DATA0_XI         (6L<<0)
1909 #define BNX2_NVM_STATUS_SPI_FSM_STATE_SPI_WRITE_DATA1_XI         (7L<<0)
1910 #define BNX2_NVM_STATUS_SPI_FSM_STATE_SPI_WRITE_DATA2_XI         (8L<<0)
1911 #define BNX2_NVM_STATUS_SPI_FSM_STATE_SPI_READ_DATA0_XI  (9L<<0)
1912 #define BNX2_NVM_STATUS_SPI_FSM_STATE_SPI_READ_DATA1_XI  (10L<<0)
1913 #define BNX2_NVM_STATUS_SPI_FSM_STATE_SPI_READ_DATA2_XI  (11L<<0)
1914 #define BNX2_NVM_STATUS_SPI_FSM_STATE_SPI_READ_STATUS_RDID0_XI   (12L<<0)
1915 #define BNX2_NVM_STATUS_SPI_FSM_STATE_SPI_READ_STATUS_RDID1_XI   (13L<<0)
1916 #define BNX2_NVM_STATUS_SPI_FSM_STATE_SPI_READ_STATUS_RDID2_XI   (14L<<0)
1917 #define BNX2_NVM_STATUS_SPI_FSM_STATE_SPI_READ_STATUS_RDID3_XI   (15L<<0)
1918 #define BNX2_NVM_STATUS_SPI_FSM_STATE_SPI_READ_STATUS_RDID4_XI   (16L<<0)
1919 #define BNX2_NVM_STATUS_SPI_FSM_STATE_SPI_CHECK_BUSY0_XI         (17L<<0)
1920 #define BNX2_NVM_STATUS_SPI_FSM_STATE_SPI_ST_WREN_XI     (18L<<0)
1921 #define BNX2_NVM_STATUS_SPI_FSM_STATE_SPI_WAIT_XI        (19L<<0)
1922 
1923 #define BNX2_NVM_WRITE                  0x00006408
1924 #define BNX2_NVM_WRITE_NVM_WRITE_VALUE                   (0xffffffffL<<0)
1925 #define BNX2_NVM_WRITE_NVM_WRITE_VALUE_BIT_BANG          (0L<<0)
1926 #define BNX2_NVM_WRITE_NVM_WRITE_VALUE_EECLK             (1L<<0)
1927 #define BNX2_NVM_WRITE_NVM_WRITE_VALUE_EEDATA            (2L<<0)
1928 #define BNX2_NVM_WRITE_NVM_WRITE_VALUE_SCLK              (4L<<0)
1929 #define BNX2_NVM_WRITE_NVM_WRITE_VALUE_CS_B              (8L<<0)
1930 #define BNX2_NVM_WRITE_NVM_WRITE_VALUE_SO                (16L<<0)
1931 #define BNX2_NVM_WRITE_NVM_WRITE_VALUE_SI                (32L<<0)
1932 #define BNX2_NVM_WRITE_NVM_WRITE_VALUE_SI_XI             (1L<<0)
1933 #define BNX2_NVM_WRITE_NVM_WRITE_VALUE_SO_XI             (2L<<0)
1934 #define BNX2_NVM_WRITE_NVM_WRITE_VALUE_CS_B_XI           (4L<<0)
1935 #define BNX2_NVM_WRITE_NVM_WRITE_VALUE_SCLK_XI           (8L<<0)
1936 
1937 #define BNX2_NVM_ADDR                   0x0000640c
1938 #define BNX2_NVM_ADDR_NVM_ADDR_VALUE                     (0xffffffL<<0)
1939 #define BNX2_NVM_ADDR_NVM_ADDR_VALUE_BIT_BANG            (0L<<0)
1940 #define BNX2_NVM_ADDR_NVM_ADDR_VALUE_EECLK               (1L<<0)
1941 #define BNX2_NVM_ADDR_NVM_ADDR_VALUE_EEDATA              (2L<<0)
1942 #define BNX2_NVM_ADDR_NVM_ADDR_VALUE_SCLK                (4L<<0)
1943 #define BNX2_NVM_ADDR_NVM_ADDR_VALUE_CS_B                (8L<<0)
1944 #define BNX2_NVM_ADDR_NVM_ADDR_VALUE_SO                  (16L<<0)
1945 #define BNX2_NVM_ADDR_NVM_ADDR_VALUE_SI                  (32L<<0)
1946 #define BNX2_NVM_ADDR_NVM_ADDR_VALUE_SI_XI               (1L<<0)
1947 #define BNX2_NVM_ADDR_NVM_ADDR_VALUE_SO_XI               (2L<<0)
1948 #define BNX2_NVM_ADDR_NVM_ADDR_VALUE_CS_B_XI             (4L<<0)
1949 #define BNX2_NVM_ADDR_NVM_ADDR_VALUE_SCLK_XI             (8L<<0)
1950 
1951 #define BNX2_NVM_READ                   0x00006410
1952 #define BNX2_NVM_READ_NVM_READ_VALUE                     (0xffffffffL<<0)
1953 #define BNX2_NVM_READ_NVM_READ_VALUE_BIT_BANG            (0L<<0)
1954 #define BNX2_NVM_READ_NVM_READ_VALUE_EECLK               (1L<<0)
1955 #define BNX2_NVM_READ_NVM_READ_VALUE_EEDATA              (2L<<0)
1956 #define BNX2_NVM_READ_NVM_READ_VALUE_SCLK                (4L<<0)
1957 #define BNX2_NVM_READ_NVM_READ_VALUE_CS_B                (8L<<0)
1958 #define BNX2_NVM_READ_NVM_READ_VALUE_SO                  (16L<<0)
1959 #define BNX2_NVM_READ_NVM_READ_VALUE_SI                  (32L<<0)
1960 #define BNX2_NVM_READ_NVM_READ_VALUE_SI_XI               (1L<<0)
1961 #define BNX2_NVM_READ_NVM_READ_VALUE_SO_XI               (2L<<0)
1962 #define BNX2_NVM_READ_NVM_READ_VALUE_CS_B_XI             (4L<<0)
1963 #define BNX2_NVM_READ_NVM_READ_VALUE_SCLK_XI             (8L<<0)
1964 
1965 #define BNX2_NVM_CFG1                   0x00006414
1966 #define BNX2_NVM_CFG1_FLASH_MODE                         (1L<<0)
1967 #define BNX2_NVM_CFG1_BUFFER_MODE                        (1L<<1)
1968 #define BNX2_NVM_CFG1_PASS_MODE                          (1L<<2)
1969 #define BNX2_NVM_CFG1_BITBANG_MODE                       (1L<<3)
1970 #define BNX2_NVM_CFG1_STATUS_BIT                         (0x7L<<4)
1971 #define BNX2_NVM_CFG1_STATUS_BIT_FLASH_RDY               (0L<<4)
1972 #define BNX2_NVM_CFG1_STATUS_BIT_BUFFER_RDY              (7L<<4)
1973 #define BNX2_NVM_CFG1_SPI_CLK_DIV                        (0xfL<<7)
1974 #define BNX2_NVM_CFG1_SEE_CLK_DIV                        (0x7ffL<<11)
1975 #define BNX2_NVM_CFG1_STRAP_CONTROL_0                    (1L<<23)
1976 #define BNX2_NVM_CFG1_PROTECT_MODE                       (1L<<24)
1977 #define BNX2_NVM_CFG1_FLASH_SIZE                         (1L<<25)
1978 #define BNX2_NVM_CFG1_FW_USTRAP_1                        (1L<<26)
1979 #define BNX2_NVM_CFG1_FW_USTRAP_0                        (1L<<27)
1980 #define BNX2_NVM_CFG1_FW_USTRAP_2                        (1L<<28)
1981 #define BNX2_NVM_CFG1_FW_USTRAP_3                        (1L<<29)
1982 #define BNX2_NVM_CFG1_FW_FLASH_TYPE_EN                   (1L<<30)
1983 #define BNX2_NVM_CFG1_COMPAT_BYPASSS                     (1L<<31)
1984 
1985 #define BNX2_NVM_CFG2                   0x00006418
1986 #define BNX2_NVM_CFG2_ERASE_CMD                          (0xffL<<0)
1987 #define BNX2_NVM_CFG2_DUMMY                              (0xffL<<8)
1988 #define BNX2_NVM_CFG2_STATUS_CMD                         (0xffL<<16)
1989 #define BNX2_NVM_CFG2_READ_ID                            (0xffL<<24)
1990 
1991 #define BNX2_NVM_CFG3                   0x0000641c
1992 #define BNX2_NVM_CFG3_BUFFER_RD_CMD                      (0xffL<<0)
1993 #define BNX2_NVM_CFG3_WRITE_CMD                          (0xffL<<8)
1994 #define BNX2_NVM_CFG3_BUFFER_WRITE_CMD                   (0xffL<<16)
1995 #define BNX2_NVM_CFG3_READ_CMD                           (0xffL<<24)
1996 
1997 #define BNX2_NVM_SW_ARB                 0x00006420
1998 #define BNX2_NVM_SW_ARB_ARB_REQ_SET0                     (1L<<0)
1999 #define BNX2_NVM_SW_ARB_ARB_REQ_SET1                     (1L<<1)
2000 #define BNX2_NVM_SW_ARB_ARB_REQ_SET2                     (1L<<2)
2001 #define BNX2_NVM_SW_ARB_ARB_REQ_SET3                     (1L<<3)
2002 #define BNX2_NVM_SW_ARB_ARB_REQ_CLR0                     (1L<<4)
2003 #define BNX2_NVM_SW_ARB_ARB_REQ_CLR1                     (1L<<5)
2004 #define BNX2_NVM_SW_ARB_ARB_REQ_CLR2                     (1L<<6)
2005 #define BNX2_NVM_SW_ARB_ARB_REQ_CLR3                     (1L<<7)
2006 #define BNX2_NVM_SW_ARB_ARB_ARB0                         (1L<<8)
2007 #define BNX2_NVM_SW_ARB_ARB_ARB1                         (1L<<9)
2008 #define BNX2_NVM_SW_ARB_ARB_ARB2                         (1L<<10)
2009 #define BNX2_NVM_SW_ARB_ARB_ARB3                         (1L<<11)
2010 #define BNX2_NVM_SW_ARB_REQ0                             (1L<<12)
2011 #define BNX2_NVM_SW_ARB_REQ1                             (1L<<13)
2012 #define BNX2_NVM_SW_ARB_REQ2                             (1L<<14)
2013 #define BNX2_NVM_SW_ARB_REQ3                             (1L<<15)
2014 
2015 #define BNX2_NVM_ACCESS_ENABLE              0x00006424
2016 #define BNX2_NVM_ACCESS_ENABLE_EN                        (1L<<0)
2017 #define BNX2_NVM_ACCESS_ENABLE_WR_EN                     (1L<<1)
2018 
2019 #define BNX2_NVM_WRITE1                 0x00006428
2020 #define BNX2_NVM_WRITE1_WREN_CMD                         (0xffL<<0)
2021 #define BNX2_NVM_WRITE1_WRDI_CMD                         (0xffL<<8)
2022 #define BNX2_NVM_WRITE1_SR_DATA                          (0xffL<<16)
2023 
2024 #define BNX2_NVM_CFG4                   0x0000642c
2025 #define BNX2_NVM_CFG4_FLASH_SIZE                         (0x7L<<0)
2026 #define BNX2_NVM_CFG4_FLASH_SIZE_1MBIT                   (0L<<0)
2027 #define BNX2_NVM_CFG4_FLASH_SIZE_2MBIT                   (1L<<0)
2028 #define BNX2_NVM_CFG4_FLASH_SIZE_4MBIT                   (2L<<0)
2029 #define BNX2_NVM_CFG4_FLASH_SIZE_8MBIT                   (3L<<0)
2030 #define BNX2_NVM_CFG4_FLASH_SIZE_16MBIT                  (4L<<0)
2031 #define BNX2_NVM_CFG4_FLASH_SIZE_32MBIT                  (5L<<0)
2032 #define BNX2_NVM_CFG4_FLASH_SIZE_64MBIT                  (6L<<0)
2033 #define BNX2_NVM_CFG4_FLASH_SIZE_128MBIT                 (7L<<0)
2034 #define BNX2_NVM_CFG4_FLASH_VENDOR                       (1L<<3)
2035 #define BNX2_NVM_CFG4_FLASH_VENDOR_ST                    (0L<<3)
2036 #define BNX2_NVM_CFG4_FLASH_VENDOR_ATMEL                 (1L<<3)
2037 #define BNX2_NVM_CFG4_MODE_256_EMPTY_BIT_LOC             (0x3L<<4)
2038 #define BNX2_NVM_CFG4_MODE_256_EMPTY_BIT_LOC_BIT8        (0L<<4)
2039 #define BNX2_NVM_CFG4_MODE_256_EMPTY_BIT_LOC_BIT9        (1L<<4)
2040 #define BNX2_NVM_CFG4_MODE_256_EMPTY_BIT_LOC_BIT10       (2L<<4)
2041 #define BNX2_NVM_CFG4_MODE_256_EMPTY_BIT_LOC_BIT11       (3L<<4)
2042 #define BNX2_NVM_CFG4_STATUS_BIT_POLARITY                (1L<<6)
2043 #define BNX2_NVM_CFG4_RESERVED                           (0x1ffffffL<<7)
2044 
2045 #define BNX2_NVM_RECONFIG               0x00006430
2046 #define BNX2_NVM_RECONFIG_ORIG_STRAP_VALUE               (0xfL<<0)
2047 #define BNX2_NVM_RECONFIG_ORIG_STRAP_VALUE_ST            (0L<<0)
2048 #define BNX2_NVM_RECONFIG_ORIG_STRAP_VALUE_ATMEL         (1L<<0)
2049 #define BNX2_NVM_RECONFIG_RECONFIG_STRAP_VALUE           (0xfL<<4)
2050 #define BNX2_NVM_RECONFIG_RESERVED                       (0x7fffffL<<8)
2051 #define BNX2_NVM_RECONFIG_RECONFIG_DONE                  (1L<<31)
2052 
2053 
2054 
2055 /*
2056  *  dma_reg definition
2057  *  offset: 0xc00
2058  */
2059 #define BNX2_DMA_COMMAND                0x00000c00
2060 #define BNX2_DMA_COMMAND_ENABLE                          (1L<<0)
2061 
2062 #define BNX2_DMA_STATUS                 0x00000c04
2063 #define BNX2_DMA_STATUS_PAR_ERROR_STATE                  (1L<<0)
2064 #define BNX2_DMA_STATUS_READ_TRANSFERS_STAT              (1L<<16)
2065 #define BNX2_DMA_STATUS_READ_DELAY_PCI_CLKS_STAT         (1L<<17)
2066 #define BNX2_DMA_STATUS_BIG_READ_TRANSFERS_STAT          (1L<<18)
2067 #define BNX2_DMA_STATUS_BIG_READ_DELAY_PCI_CLKS_STAT     (1L<<19)
2068 #define BNX2_DMA_STATUS_BIG_READ_RETRY_AFTER_DATA_STAT   (1L<<20)
2069 #define BNX2_DMA_STATUS_WRITE_TRANSFERS_STAT             (1L<<21)
2070 #define BNX2_DMA_STATUS_WRITE_DELAY_PCI_CLKS_STAT        (1L<<22)
2071 #define BNX2_DMA_STATUS_BIG_WRITE_TRANSFERS_STAT         (1L<<23)
2072 #define BNX2_DMA_STATUS_BIG_WRITE_DELAY_PCI_CLKS_STAT    (1L<<24)
2073 #define BNX2_DMA_STATUS_BIG_WRITE_RETRY_AFTER_DATA_STAT  (1L<<25)
2074 #define BNX2_DMA_STATUS_GLOBAL_ERR_XI                    (1L<<0)
2075 #define BNX2_DMA_STATUS_BME_XI                           (1L<<4)
2076 
2077 #define BNX2_DMA_CONFIG                 0x00000c08
2078 #define BNX2_DMA_CONFIG_DATA_BYTE_SWAP                   (1L<<0)
2079 #define BNX2_DMA_CONFIG_DATA_WORD_SWAP                   (1L<<1)
2080 #define BNX2_DMA_CONFIG_CNTL_BYTE_SWAP                   (1L<<4)
2081 #define BNX2_DMA_CONFIG_CNTL_WORD_SWAP                   (1L<<5)
2082 #define BNX2_DMA_CONFIG_ONE_DMA                          (1L<<6)
2083 #define BNX2_DMA_CONFIG_CNTL_TWO_DMA                     (1L<<7)
2084 #define BNX2_DMA_CONFIG_CNTL_FPGA_MODE                   (1L<<8)
2085 #define BNX2_DMA_CONFIG_CNTL_PING_PONG_DMA               (1L<<10)
2086 #define BNX2_DMA_CONFIG_CNTL_PCI_COMP_DLY                (1L<<11)
2087 #define BNX2_DMA_CONFIG_NO_RCHANS_IN_USE                 (0xfL<<12)
2088 #define BNX2_DMA_CONFIG_NO_WCHANS_IN_USE                 (0xfL<<16)
2089 #define BNX2_DMA_CONFIG_PCI_CLK_CMP_BITS                 (0x7L<<20)
2090 #define BNX2_DMA_CONFIG_PCI_FAST_CLK_CMP                 (1L<<23)
2091 #define BNX2_DMA_CONFIG_BIG_SIZE                         (0xfL<<24)
2092 #define BNX2_DMA_CONFIG_BIG_SIZE_NONE                    (0x0L<<24)
2093 #define BNX2_DMA_CONFIG_BIG_SIZE_64                      (0x1L<<24)
2094 #define BNX2_DMA_CONFIG_BIG_SIZE_128                     (0x2L<<24)
2095 #define BNX2_DMA_CONFIG_BIG_SIZE_256                     (0x4L<<24)
2096 #define BNX2_DMA_CONFIG_BIG_SIZE_512                     (0x8L<<24)
2097 #define BNX2_DMA_CONFIG_DAT_WBSWAP_MODE_XI               (0x3L<<0)
2098 #define BNX2_DMA_CONFIG_CTL_WBSWAP_MODE_XI               (0x3L<<4)
2099 #define BNX2_DMA_CONFIG_MAX_PL_XI                        (0x7L<<12)
2100 #define BNX2_DMA_CONFIG_MAX_PL_128B_XI                   (0L<<12)
2101 #define BNX2_DMA_CONFIG_MAX_PL_256B_XI                   (1L<<12)
2102 #define BNX2_DMA_CONFIG_MAX_PL_512B_XI                   (2L<<12)
2103 #define BNX2_DMA_CONFIG_MAX_PL_EN_XI                     (1L<<15)
2104 #define BNX2_DMA_CONFIG_MAX_RRS_XI                       (0x7L<<16)
2105 #define BNX2_DMA_CONFIG_MAX_RRS_128B_XI                  (0L<<16)
2106 #define BNX2_DMA_CONFIG_MAX_RRS_256B_XI                  (1L<<16)
2107 #define BNX2_DMA_CONFIG_MAX_RRS_512B_XI                  (2L<<16)
2108 #define BNX2_DMA_CONFIG_MAX_RRS_1024B_XI                 (3L<<16)
2109 #define BNX2_DMA_CONFIG_MAX_RRS_2048B_XI                 (4L<<16)
2110 #define BNX2_DMA_CONFIG_MAX_RRS_4096B_XI                 (5L<<16)
2111 #define BNX2_DMA_CONFIG_MAX_RRS_EN_XI                    (1L<<19)
2112 #define BNX2_DMA_CONFIG_NO_64SWAP_EN_XI                  (1L<<31)
2113 
2114 #define BNX2_DMA_BLACKOUT               0x00000c0c
2115 #define BNX2_DMA_BLACKOUT_RD_RETRY_BLACKOUT              (0xffL<<0)
2116 #define BNX2_DMA_BLACKOUT_2ND_RD_RETRY_BLACKOUT          (0xffL<<8)
2117 #define BNX2_DMA_BLACKOUT_WR_RETRY_BLACKOUT              (0xffL<<16)
2118 
2119 #define BNX2_DMA_READ_MASTER_SETTING_0          0x00000c10
2120 #define BNX2_DMA_READ_MASTER_SETTING_0_TBDC_NO_SNOOP     (1L<<0)
2121 #define BNX2_DMA_READ_MASTER_SETTING_0_TBDC_RELAX_ORDER  (1L<<1)
2122 #define BNX2_DMA_READ_MASTER_SETTING_0_TBDC_PRIORITY     (1L<<2)
2123 #define BNX2_DMA_READ_MASTER_SETTING_0_TBDC_TRAFFIC_CLASS        (0x7L<<4)
2124 #define BNX2_DMA_READ_MASTER_SETTING_0_TBDC_PARAM_EN     (1L<<7)
2125 #define BNX2_DMA_READ_MASTER_SETTING_0_RBDC_NO_SNOOP     (1L<<8)
2126 #define BNX2_DMA_READ_MASTER_SETTING_0_RBDC_RELAX_ORDER  (1L<<9)
2127 #define BNX2_DMA_READ_MASTER_SETTING_0_RBDC_PRIORITY     (1L<<10)
2128 #define BNX2_DMA_READ_MASTER_SETTING_0_RBDC_TRAFFIC_CLASS        (0x7L<<12)
2129 #define BNX2_DMA_READ_MASTER_SETTING_0_RBDC_PARAM_EN     (1L<<15)
2130 #define BNX2_DMA_READ_MASTER_SETTING_0_TDMA_NO_SNOOP     (1L<<16)
2131 #define BNX2_DMA_READ_MASTER_SETTING_0_TDMA_RELAX_ORDER  (1L<<17)
2132 #define BNX2_DMA_READ_MASTER_SETTING_0_TDMA_PRIORITY     (1L<<18)
2133 #define BNX2_DMA_READ_MASTER_SETTING_0_TDMA_TRAFFIC_CLASS        (0x7L<<20)
2134 #define BNX2_DMA_READ_MASTER_SETTING_0_TDMA_PARAM_EN     (1L<<23)
2135 #define BNX2_DMA_READ_MASTER_SETTING_0_CTX_NO_SNOOP      (1L<<24)
2136 #define BNX2_DMA_READ_MASTER_SETTING_0_CTX_RELAX_ORDER   (1L<<25)
2137 #define BNX2_DMA_READ_MASTER_SETTING_0_CTX_PRIORITY      (1L<<26)
2138 #define BNX2_DMA_READ_MASTER_SETTING_0_CTX_TRAFFIC_CLASS         (0x7L<<28)
2139 #define BNX2_DMA_READ_MASTER_SETTING_0_CTX_PARAM_EN      (1L<<31)
2140 
2141 #define BNX2_DMA_READ_MASTER_SETTING_1          0x00000c14
2142 #define BNX2_DMA_READ_MASTER_SETTING_1_COM_NO_SNOOP      (1L<<0)
2143 #define BNX2_DMA_READ_MASTER_SETTING_1_COM_RELAX_ORDER   (1L<<1)
2144 #define BNX2_DMA_READ_MASTER_SETTING_1_COM_PRIORITY      (1L<<2)
2145 #define BNX2_DMA_READ_MASTER_SETTING_1_COM_TRAFFIC_CLASS         (0x7L<<4)
2146 #define BNX2_DMA_READ_MASTER_SETTING_1_COM_PARAM_EN      (1L<<7)
2147 #define BNX2_DMA_READ_MASTER_SETTING_1_CP_NO_SNOOP       (1L<<8)
2148 #define BNX2_DMA_READ_MASTER_SETTING_1_CP_RELAX_ORDER    (1L<<9)
2149 #define BNX2_DMA_READ_MASTER_SETTING_1_CP_PRIORITY       (1L<<10)
2150 #define BNX2_DMA_READ_MASTER_SETTING_1_CP_TRAFFIC_CLASS  (0x7L<<12)
2151 #define BNX2_DMA_READ_MASTER_SETTING_1_CP_PARAM_EN       (1L<<15)
2152 
2153 #define BNX2_DMA_WRITE_MASTER_SETTING_0         0x00000c18
2154 #define BNX2_DMA_WRITE_MASTER_SETTING_0_HC_NO_SNOOP      (1L<<0)
2155 #define BNX2_DMA_WRITE_MASTER_SETTING_0_HC_RELAX_ORDER   (1L<<1)
2156 #define BNX2_DMA_WRITE_MASTER_SETTING_0_HC_PRIORITY      (1L<<2)
2157 #define BNX2_DMA_WRITE_MASTER_SETTING_0_HC_CS_VLD        (1L<<3)
2158 #define BNX2_DMA_WRITE_MASTER_SETTING_0_HC_TRAFFIC_CLASS         (0x7L<<4)
2159 #define BNX2_DMA_WRITE_MASTER_SETTING_0_HC_PARAM_EN      (1L<<7)
2160 #define BNX2_DMA_WRITE_MASTER_SETTING_0_RDMA_NO_SNOOP    (1L<<8)
2161 #define BNX2_DMA_WRITE_MASTER_SETTING_0_RDMA_RELAX_ORDER         (1L<<9)
2162 #define BNX2_DMA_WRITE_MASTER_SETTING_0_RDMA_PRIORITY    (1L<<10)
2163 #define BNX2_DMA_WRITE_MASTER_SETTING_0_RDMA_CS_VLD      (1L<<11)
2164 #define BNX2_DMA_WRITE_MASTER_SETTING_0_RDMA_TRAFFIC_CLASS       (0x7L<<12)
2165 #define BNX2_DMA_WRITE_MASTER_SETTING_0_RDMA_PARAM_EN    (1L<<15)
2166 #define BNX2_DMA_WRITE_MASTER_SETTING_0_CTX_NO_SNOOP     (1L<<24)
2167 #define BNX2_DMA_WRITE_MASTER_SETTING_0_CTX_RELAX_ORDER  (1L<<25)
2168 #define BNX2_DMA_WRITE_MASTER_SETTING_0_CTX_PRIORITY     (1L<<26)
2169 #define BNX2_DMA_WRITE_MASTER_SETTING_0_CTX_CS_VLD       (1L<<27)
2170 #define BNX2_DMA_WRITE_MASTER_SETTING_0_CTX_TRAFFIC_CLASS        (0x7L<<28)
2171 #define BNX2_DMA_WRITE_MASTER_SETTING_0_CTX_PARAM_EN     (1L<<31)
2172 
2173 #define BNX2_DMA_WRITE_MASTER_SETTING_1         0x00000c1c
2174 #define BNX2_DMA_WRITE_MASTER_SETTING_1_COM_NO_SNOOP     (1L<<0)
2175 #define BNX2_DMA_WRITE_MASTER_SETTING_1_COM_RELAX_ORDER  (1L<<1)
2176 #define BNX2_DMA_WRITE_MASTER_SETTING_1_COM_PRIORITY     (1L<<2)
2177 #define BNX2_DMA_WRITE_MASTER_SETTING_1_COM_CS_VLD       (1L<<3)
2178 #define BNX2_DMA_WRITE_MASTER_SETTING_1_COM_TRAFFIC_CLASS        (0x7L<<4)
2179 #define BNX2_DMA_WRITE_MASTER_SETTING_1_COM_PARAM_EN     (1L<<7)
2180 #define BNX2_DMA_WRITE_MASTER_SETTING_1_CP_NO_SNOOP      (1L<<8)
2181 #define BNX2_DMA_WRITE_MASTER_SETTING_1_CP_RELAX_ORDER   (1L<<9)
2182 #define BNX2_DMA_WRITE_MASTER_SETTING_1_CP_PRIORITY      (1L<<10)
2183 #define BNX2_DMA_WRITE_MASTER_SETTING_1_CP_CS_VLD        (1L<<11)
2184 #define BNX2_DMA_WRITE_MASTER_SETTING_1_CP_TRAFFIC_CLASS         (0x7L<<12)
2185 #define BNX2_DMA_WRITE_MASTER_SETTING_1_CP_PARAM_EN      (1L<<15)
2186 
2187 #define BNX2_DMA_ARBITER                0x00000c20
2188 #define BNX2_DMA_ARBITER_NUM_READS                       (0x7L<<0)
2189 #define BNX2_DMA_ARBITER_WR_ARB_MODE                     (1L<<4)
2190 #define BNX2_DMA_ARBITER_WR_ARB_MODE_STRICT              (0L<<4)
2191 #define BNX2_DMA_ARBITER_WR_ARB_MODE_RND_RBN             (1L<<4)
2192 #define BNX2_DMA_ARBITER_RD_ARB_MODE                     (0x3L<<5)
2193 #define BNX2_DMA_ARBITER_RD_ARB_MODE_STRICT              (0L<<5)
2194 #define BNX2_DMA_ARBITER_RD_ARB_MODE_RND_RBN             (1L<<5)
2195 #define BNX2_DMA_ARBITER_RD_ARB_MODE_WGT_RND_RBN         (2L<<5)
2196 #define BNX2_DMA_ARBITER_ALT_MODE_EN                     (1L<<8)
2197 #define BNX2_DMA_ARBITER_RR_MODE                         (1L<<9)
2198 #define BNX2_DMA_ARBITER_TIMER_MODE                      (1L<<10)
2199 #define BNX2_DMA_ARBITER_OUSTD_READ_REQ                  (0xfL<<12)
2200 
2201 #define BNX2_DMA_ARB_TIMERS             0x00000c24
2202 #define BNX2_DMA_ARB_TIMERS_RD_DRR_WAIT_TIME             (0xffL<<0)
2203 #define BNX2_DMA_ARB_TIMERS_TM_MIN_TIMEOUT               (0xffL<<12)
2204 #define BNX2_DMA_ARB_TIMERS_TM_MAX_TIMEOUT               (0xfffL<<20)
2205 
2206 #define BNX2_DMA_DEBUG_VECT_PEEK            0x00000c2c
2207 #define BNX2_DMA_DEBUG_VECT_PEEK_1_VALUE                 (0x7ffL<<0)
2208 #define BNX2_DMA_DEBUG_VECT_PEEK_1_PEEK_EN               (1L<<11)
2209 #define BNX2_DMA_DEBUG_VECT_PEEK_1_SEL                   (0xfL<<12)
2210 #define BNX2_DMA_DEBUG_VECT_PEEK_2_VALUE                 (0x7ffL<<16)
2211 #define BNX2_DMA_DEBUG_VECT_PEEK_2_PEEK_EN               (1L<<27)
2212 #define BNX2_DMA_DEBUG_VECT_PEEK_2_SEL                   (0xfL<<28)
2213 
2214 #define BNX2_DMA_TAG_RAM_00             0x00000c30
2215 #define BNX2_DMA_TAG_RAM_00_CHANNEL                      (0xfL<<0)
2216 #define BNX2_DMA_TAG_RAM_00_MASTER                       (0x7L<<4)
2217 #define BNX2_DMA_TAG_RAM_00_MASTER_CTX                   (0L<<4)
2218 #define BNX2_DMA_TAG_RAM_00_MASTER_RBDC                  (1L<<4)
2219 #define BNX2_DMA_TAG_RAM_00_MASTER_TBDC                  (2L<<4)
2220 #define BNX2_DMA_TAG_RAM_00_MASTER_COM                   (3L<<4)
2221 #define BNX2_DMA_TAG_RAM_00_MASTER_CP                    (4L<<4)
2222 #define BNX2_DMA_TAG_RAM_00_MASTER_TDMA                  (5L<<4)
2223 #define BNX2_DMA_TAG_RAM_00_SWAP                         (0x3L<<7)
2224 #define BNX2_DMA_TAG_RAM_00_SWAP_CONFIG                  (0L<<7)
2225 #define BNX2_DMA_TAG_RAM_00_SWAP_DATA                    (1L<<7)
2226 #define BNX2_DMA_TAG_RAM_00_SWAP_CONTROL                 (2L<<7)
2227 #define BNX2_DMA_TAG_RAM_00_FUNCTION                     (1L<<9)
2228 #define BNX2_DMA_TAG_RAM_00_VALID                        (1L<<10)
2229 
2230 #define BNX2_DMA_TAG_RAM_01             0x00000c34
2231 #define BNX2_DMA_TAG_RAM_01_CHANNEL                      (0xfL<<0)
2232 #define BNX2_DMA_TAG_RAM_01_MASTER                       (0x7L<<4)
2233 #define BNX2_DMA_TAG_RAM_01_MASTER_CTX                   (0L<<4)
2234 #define BNX2_DMA_TAG_RAM_01_MASTER_RBDC                  (1L<<4)
2235 #define BNX2_DMA_TAG_RAM_01_MASTER_TBDC                  (2L<<4)
2236 #define BNX2_DMA_TAG_RAM_01_MASTER_COM                   (3L<<4)
2237 #define BNX2_DMA_TAG_RAM_01_MASTER_CP                    (4L<<4)
2238 #define BNX2_DMA_TAG_RAM_01_MASTER_TDMA                  (5L<<4)
2239 #define BNX2_DMA_TAG_RAM_01_SWAP                         (0x3L<<7)
2240 #define BNX2_DMA_TAG_RAM_01_SWAP_CONFIG                  (0L<<7)
2241 #define BNX2_DMA_TAG_RAM_01_SWAP_DATA                    (1L<<7)
2242 #define BNX2_DMA_TAG_RAM_01_SWAP_CONTROL                 (2L<<7)
2243 #define BNX2_DMA_TAG_RAM_01_FUNCTION                     (1L<<9)
2244 #define BNX2_DMA_TAG_RAM_01_VALID                        (1L<<10)
2245 
2246 #define BNX2_DMA_TAG_RAM_02             0x00000c38
2247 #define BNX2_DMA_TAG_RAM_02_CHANNEL                      (0xfL<<0)
2248 #define BNX2_DMA_TAG_RAM_02_MASTER                       (0x7L<<4)
2249 #define BNX2_DMA_TAG_RAM_02_MASTER_CTX                   (0L<<4)
2250 #define BNX2_DMA_TAG_RAM_02_MASTER_RBDC                  (1L<<4)
2251 #define BNX2_DMA_TAG_RAM_02_MASTER_TBDC                  (2L<<4)
2252 #define BNX2_DMA_TAG_RAM_02_MASTER_COM                   (3L<<4)
2253 #define BNX2_DMA_TAG_RAM_02_MASTER_CP                    (4L<<4)
2254 #define BNX2_DMA_TAG_RAM_02_MASTER_TDMA                  (5L<<4)
2255 #define BNX2_DMA_TAG_RAM_02_SWAP                         (0x3L<<7)
2256 #define BNX2_DMA_TAG_RAM_02_SWAP_CONFIG                  (0L<<7)
2257 #define BNX2_DMA_TAG_RAM_02_SWAP_DATA                    (1L<<7)
2258 #define BNX2_DMA_TAG_RAM_02_SWAP_CONTROL                 (2L<<7)
2259 #define BNX2_DMA_TAG_RAM_02_FUNCTION                     (1L<<9)
2260 #define BNX2_DMA_TAG_RAM_02_VALID                        (1L<<10)
2261 
2262 #define BNX2_DMA_TAG_RAM_03             0x00000c3c
2263 #define BNX2_DMA_TAG_RAM_03_CHANNEL                      (0xfL<<0)
2264 #define BNX2_DMA_TAG_RAM_03_MASTER                       (0x7L<<4)
2265 #define BNX2_DMA_TAG_RAM_03_MASTER_CTX                   (0L<<4)
2266 #define BNX2_DMA_TAG_RAM_03_MASTER_RBDC                  (1L<<4)
2267 #define BNX2_DMA_TAG_RAM_03_MASTER_TBDC                  (2L<<4)
2268 #define BNX2_DMA_TAG_RAM_03_MASTER_COM                   (3L<<4)
2269 #define BNX2_DMA_TAG_RAM_03_MASTER_CP                    (4L<<4)
2270 #define BNX2_DMA_TAG_RAM_03_MASTER_TDMA                  (5L<<4)
2271 #define BNX2_DMA_TAG_RAM_03_SWAP                         (0x3L<<7)
2272 #define BNX2_DMA_TAG_RAM_03_SWAP_CONFIG                  (0L<<7)
2273 #define BNX2_DMA_TAG_RAM_03_SWAP_DATA                    (1L<<7)
2274 #define BNX2_DMA_TAG_RAM_03_SWAP_CONTROL                 (2L<<7)
2275 #define BNX2_DMA_TAG_RAM_03_FUNCTION                     (1L<<9)
2276 #define BNX2_DMA_TAG_RAM_03_VALID                        (1L<<10)
2277 
2278 #define BNX2_DMA_TAG_RAM_04             0x00000c40
2279 #define BNX2_DMA_TAG_RAM_04_CHANNEL                      (0xfL<<0)
2280 #define BNX2_DMA_TAG_RAM_04_MASTER                       (0x7L<<4)
2281 #define BNX2_DMA_TAG_RAM_04_MASTER_CTX                   (0L<<4)
2282 #define BNX2_DMA_TAG_RAM_04_MASTER_RBDC                  (1L<<4)
2283 #define BNX2_DMA_TAG_RAM_04_MASTER_TBDC                  (2L<<4)
2284 #define BNX2_DMA_TAG_RAM_04_MASTER_COM                   (3L<<4)
2285 #define BNX2_DMA_TAG_RAM_04_MASTER_CP                    (4L<<4)
2286 #define BNX2_DMA_TAG_RAM_04_MASTER_TDMA                  (5L<<4)
2287 #define BNX2_DMA_TAG_RAM_04_SWAP                         (0x3L<<7)
2288 #define BNX2_DMA_TAG_RAM_04_SWAP_CONFIG                  (0L<<7)
2289 #define BNX2_DMA_TAG_RAM_04_SWAP_DATA                    (1L<<7)
2290 #define BNX2_DMA_TAG_RAM_04_SWAP_CONTROL                 (2L<<7)
2291 #define BNX2_DMA_TAG_RAM_04_FUNCTION                     (1L<<9)
2292 #define BNX2_DMA_TAG_RAM_04_VALID                        (1L<<10)
2293 
2294 #define BNX2_DMA_TAG_RAM_05             0x00000c44
2295 #define BNX2_DMA_TAG_RAM_05_CHANNEL                      (0xfL<<0)
2296 #define BNX2_DMA_TAG_RAM_05_MASTER                       (0x7L<<4)
2297 #define BNX2_DMA_TAG_RAM_05_MASTER_CTX                   (0L<<4)
2298 #define BNX2_DMA_TAG_RAM_05_MASTER_RBDC                  (1L<<4)
2299 #define BNX2_DMA_TAG_RAM_05_MASTER_TBDC                  (2L<<4)
2300 #define BNX2_DMA_TAG_RAM_05_MASTER_COM                   (3L<<4)
2301 #define BNX2_DMA_TAG_RAM_05_MASTER_CP                    (4L<<4)
2302 #define BNX2_DMA_TAG_RAM_05_MASTER_TDMA                  (5L<<4)
2303 #define BNX2_DMA_TAG_RAM_05_SWAP                         (0x3L<<7)
2304 #define BNX2_DMA_TAG_RAM_05_SWAP_CONFIG                  (0L<<7)
2305 #define BNX2_DMA_TAG_RAM_05_SWAP_DATA                    (1L<<7)
2306 #define BNX2_DMA_TAG_RAM_05_SWAP_CONTROL                 (2L<<7)
2307 #define BNX2_DMA_TAG_RAM_05_FUNCTION                     (1L<<9)
2308 #define BNX2_DMA_TAG_RAM_05_VALID                        (1L<<10)
2309 
2310 #define BNX2_DMA_TAG_RAM_06             0x00000c48
2311 #define BNX2_DMA_TAG_RAM_06_CHANNEL                      (0xfL<<0)
2312 #define BNX2_DMA_TAG_RAM_06_MASTER                       (0x7L<<4)
2313 #define BNX2_DMA_TAG_RAM_06_MASTER_CTX                   (0L<<4)
2314 #define BNX2_DMA_TAG_RAM_06_MASTER_RBDC                  (1L<<4)
2315 #define BNX2_DMA_TAG_RAM_06_MASTER_TBDC                  (2L<<4)
2316 #define BNX2_DMA_TAG_RAM_06_MASTER_COM                   (3L<<4)
2317 #define BNX2_DMA_TAG_RAM_06_MASTER_CP                    (4L<<4)
2318 #define BNX2_DMA_TAG_RAM_06_MASTER_TDMA                  (5L<<4)
2319 #define BNX2_DMA_TAG_RAM_06_SWAP                         (0x3L<<7)
2320 #define BNX2_DMA_TAG_RAM_06_SWAP_CONFIG                  (0L<<7)
2321 #define BNX2_DMA_TAG_RAM_06_SWAP_DATA                    (1L<<7)
2322 #define BNX2_DMA_TAG_RAM_06_SWAP_CONTROL                 (2L<<7)
2323 #define BNX2_DMA_TAG_RAM_06_FUNCTION                     (1L<<9)
2324 #define BNX2_DMA_TAG_RAM_06_VALID                        (1L<<10)
2325 
2326 #define BNX2_DMA_TAG_RAM_07             0x00000c4c
2327 #define BNX2_DMA_TAG_RAM_07_CHANNEL                      (0xfL<<0)
2328 #define BNX2_DMA_TAG_RAM_07_MASTER                       (0x7L<<4)
2329 #define BNX2_DMA_TAG_RAM_07_MASTER_CTX                   (0L<<4)
2330 #define BNX2_DMA_TAG_RAM_07_MASTER_RBDC                  (1L<<4)
2331 #define BNX2_DMA_TAG_RAM_07_MASTER_TBDC                  (2L<<4)
2332 #define BNX2_DMA_TAG_RAM_07_MASTER_COM                   (3L<<4)
2333 #define BNX2_DMA_TAG_RAM_07_MASTER_CP                    (4L<<4)
2334 #define BNX2_DMA_TAG_RAM_07_MASTER_TDMA                  (5L<<4)
2335 #define BNX2_DMA_TAG_RAM_07_SWAP                         (0x3L<<7)
2336 #define BNX2_DMA_TAG_RAM_07_SWAP_CONFIG                  (0L<<7)
2337 #define BNX2_DMA_TAG_RAM_07_SWAP_DATA                    (1L<<7)
2338 #define BNX2_DMA_TAG_RAM_07_SWAP_CONTROL                 (2L<<7)
2339 #define BNX2_DMA_TAG_RAM_07_FUNCTION                     (1L<<9)
2340 #define BNX2_DMA_TAG_RAM_07_VALID                        (1L<<10)
2341 
2342 #define BNX2_DMA_TAG_RAM_08             0x00000c50
2343 #define BNX2_DMA_TAG_RAM_08_CHANNEL                      (0xfL<<0)
2344 #define BNX2_DMA_TAG_RAM_08_MASTER                       (0x7L<<4)
2345 #define BNX2_DMA_TAG_RAM_08_MASTER_CTX                   (0L<<4)
2346 #define BNX2_DMA_TAG_RAM_08_MASTER_RBDC                  (1L<<4)
2347 #define BNX2_DMA_TAG_RAM_08_MASTER_TBDC                  (2L<<4)
2348 #define BNX2_DMA_TAG_RAM_08_MASTER_COM                   (3L<<4)
2349 #define BNX2_DMA_TAG_RAM_08_MASTER_CP                    (4L<<4)
2350 #define BNX2_DMA_TAG_RAM_08_MASTER_TDMA                  (5L<<4)
2351 #define BNX2_DMA_TAG_RAM_08_SWAP                         (0x3L<<7)
2352 #define BNX2_DMA_TAG_RAM_08_SWAP_CONFIG                  (0L<<7)
2353 #define BNX2_DMA_TAG_RAM_08_SWAP_DATA                    (1L<<7)
2354 #define BNX2_DMA_TAG_RAM_08_SWAP_CONTROL                 (2L<<7)
2355 #define BNX2_DMA_TAG_RAM_08_FUNCTION                     (1L<<9)
2356 #define BNX2_DMA_TAG_RAM_08_VALID                        (1L<<10)
2357 
2358 #define BNX2_DMA_TAG_RAM_09             0x00000c54
2359 #define BNX2_DMA_TAG_RAM_09_CHANNEL                      (0xfL<<0)
2360 #define BNX2_DMA_TAG_RAM_09_MASTER                       (0x7L<<4)
2361 #define BNX2_DMA_TAG_RAM_09_MASTER_CTX                   (0L<<4)
2362 #define BNX2_DMA_TAG_RAM_09_MASTER_RBDC                  (1L<<4)
2363 #define BNX2_DMA_TAG_RAM_09_MASTER_TBDC                  (2L<<4)
2364 #define BNX2_DMA_TAG_RAM_09_MASTER_COM                   (3L<<4)
2365 #define BNX2_DMA_TAG_RAM_09_MASTER_CP                    (4L<<4)
2366 #define BNX2_DMA_TAG_RAM_09_MASTER_TDMA                  (5L<<4)
2367 #define BNX2_DMA_TAG_RAM_09_SWAP                         (0x3L<<7)
2368 #define BNX2_DMA_TAG_RAM_09_SWAP_CONFIG                  (0L<<7)
2369 #define BNX2_DMA_TAG_RAM_09_SWAP_DATA                    (1L<<7)
2370 #define BNX2_DMA_TAG_RAM_09_SWAP_CONTROL                 (2L<<7)
2371 #define BNX2_DMA_TAG_RAM_09_FUNCTION                     (1L<<9)
2372 #define BNX2_DMA_TAG_RAM_09_VALID                        (1L<<10)
2373 
2374 #define BNX2_DMA_TAG_RAM_10             0x00000c58
2375 #define BNX2_DMA_TAG_RAM_10_CHANNEL                      (0xfL<<0)
2376 #define BNX2_DMA_TAG_RAM_10_MASTER                       (0x7L<<4)
2377 #define BNX2_DMA_TAG_RAM_10_MASTER_CTX                   (0L<<4)
2378 #define BNX2_DMA_TAG_RAM_10_MASTER_RBDC                  (1L<<4)
2379 #define BNX2_DMA_TAG_RAM_10_MASTER_TBDC                  (2L<<4)
2380 #define BNX2_DMA_TAG_RAM_10_MASTER_COM                   (3L<<4)
2381 #define BNX2_DMA_TAG_RAM_10_MASTER_CP                    (4L<<4)
2382 #define BNX2_DMA_TAG_RAM_10_MASTER_TDMA                  (5L<<4)
2383 #define BNX2_DMA_TAG_RAM_10_SWAP                         (0x3L<<7)
2384 #define BNX2_DMA_TAG_RAM_10_SWAP_CONFIG                  (0L<<7)
2385 #define BNX2_DMA_TAG_RAM_10_SWAP_DATA                    (1L<<7)
2386 #define BNX2_DMA_TAG_RAM_10_SWAP_CONTROL                 (2L<<7)
2387 #define BNX2_DMA_TAG_RAM_10_FUNCTION                     (1L<<9)
2388 #define BNX2_DMA_TAG_RAM_10_VALID                        (1L<<10)
2389 
2390 #define BNX2_DMA_TAG_RAM_11             0x00000c5c
2391 #define BNX2_DMA_TAG_RAM_11_CHANNEL                      (0xfL<<0)
2392 #define BNX2_DMA_TAG_RAM_11_MASTER                       (0x7L<<4)
2393 #define BNX2_DMA_TAG_RAM_11_MASTER_CTX                   (0L<<4)
2394 #define BNX2_DMA_TAG_RAM_11_MASTER_RBDC                  (1L<<4)
2395 #define BNX2_DMA_TAG_RAM_11_MASTER_TBDC                  (2L<<4)
2396 #define BNX2_DMA_TAG_RAM_11_MASTER_COM                   (3L<<4)
2397 #define BNX2_DMA_TAG_RAM_11_MASTER_CP                    (4L<<4)
2398 #define BNX2_DMA_TAG_RAM_11_MASTER_TDMA                  (5L<<4)
2399 #define BNX2_DMA_TAG_RAM_11_SWAP                         (0x3L<<7)
2400 #define BNX2_DMA_TAG_RAM_11_SWAP_CONFIG                  (0L<<7)
2401 #define BNX2_DMA_TAG_RAM_11_SWAP_DATA                    (1L<<7)
2402 #define BNX2_DMA_TAG_RAM_11_SWAP_CONTROL                 (2L<<7)
2403 #define BNX2_DMA_TAG_RAM_11_FUNCTION                     (1L<<9)
2404 #define BNX2_DMA_TAG_RAM_11_VALID                        (1L<<10)
2405 
2406 #define BNX2_DMA_RCHAN_STAT_22              0x00000c60
2407 #define BNX2_DMA_RCHAN_STAT_30              0x00000c64
2408 #define BNX2_DMA_RCHAN_STAT_31              0x00000c68
2409 #define BNX2_DMA_RCHAN_STAT_32              0x00000c6c
2410 #define BNX2_DMA_RCHAN_STAT_40              0x00000c70
2411 #define BNX2_DMA_RCHAN_STAT_41              0x00000c74
2412 #define BNX2_DMA_RCHAN_STAT_42              0x00000c78
2413 #define BNX2_DMA_RCHAN_STAT_50              0x00000c7c
2414 #define BNX2_DMA_RCHAN_STAT_51              0x00000c80
2415 #define BNX2_DMA_RCHAN_STAT_52              0x00000c84
2416 #define BNX2_DMA_RCHAN_STAT_60              0x00000c88
2417 #define BNX2_DMA_RCHAN_STAT_61              0x00000c8c
2418 #define BNX2_DMA_RCHAN_STAT_62              0x00000c90
2419 #define BNX2_DMA_RCHAN_STAT_70              0x00000c94
2420 #define BNX2_DMA_RCHAN_STAT_71              0x00000c98
2421 #define BNX2_DMA_RCHAN_STAT_72              0x00000c9c
2422 #define BNX2_DMA_WCHAN_STAT_00              0x00000ca0
2423 #define BNX2_DMA_WCHAN_STAT_00_WCHAN_STA_HOST_ADDR_LOW   (0xffffffffL<<0)
2424 
2425 #define BNX2_DMA_WCHAN_STAT_01              0x00000ca4
2426 #define BNX2_DMA_WCHAN_STAT_01_WCHAN_STA_HOST_ADDR_HIGH  (0xffffffffL<<0)
2427 
2428 #define BNX2_DMA_WCHAN_STAT_02              0x00000ca8
2429 #define BNX2_DMA_WCHAN_STAT_02_LENGTH                    (0xffffL<<0)
2430 #define BNX2_DMA_WCHAN_STAT_02_WORD_SWAP                 (1L<<16)
2431 #define BNX2_DMA_WCHAN_STAT_02_BYTE_SWAP                 (1L<<17)
2432 #define BNX2_DMA_WCHAN_STAT_02_PRIORITY_LVL              (1L<<18)
2433 
2434 #define BNX2_DMA_WCHAN_STAT_10              0x00000cac
2435 #define BNX2_DMA_WCHAN_STAT_11              0x00000cb0
2436 #define BNX2_DMA_WCHAN_STAT_12              0x00000cb4
2437 #define BNX2_DMA_WCHAN_STAT_20              0x00000cb8
2438 #define BNX2_DMA_WCHAN_STAT_21              0x00000cbc
2439 #define BNX2_DMA_WCHAN_STAT_22              0x00000cc0
2440 #define BNX2_DMA_WCHAN_STAT_30              0x00000cc4
2441 #define BNX2_DMA_WCHAN_STAT_31              0x00000cc8
2442 #define BNX2_DMA_WCHAN_STAT_32              0x00000ccc
2443 #define BNX2_DMA_WCHAN_STAT_40              0x00000cd0
2444 #define BNX2_DMA_WCHAN_STAT_41              0x00000cd4
2445 #define BNX2_DMA_WCHAN_STAT_42              0x00000cd8
2446 #define BNX2_DMA_WCHAN_STAT_50              0x00000cdc
2447 #define BNX2_DMA_WCHAN_STAT_51              0x00000ce0
2448 #define BNX2_DMA_WCHAN_STAT_52              0x00000ce4
2449 #define BNX2_DMA_WCHAN_STAT_60              0x00000ce8
2450 #define BNX2_DMA_WCHAN_STAT_61              0x00000cec
2451 #define BNX2_DMA_WCHAN_STAT_62              0x00000cf0
2452 #define BNX2_DMA_WCHAN_STAT_70              0x00000cf4
2453 #define BNX2_DMA_WCHAN_STAT_71              0x00000cf8
2454 #define BNX2_DMA_WCHAN_STAT_72              0x00000cfc
2455 #define BNX2_DMA_ARB_STAT_00                0x00000d00
2456 #define BNX2_DMA_ARB_STAT_00_MASTER                      (0xffffL<<0)
2457 #define BNX2_DMA_ARB_STAT_00_MASTER_ENC                  (0xffL<<16)
2458 #define BNX2_DMA_ARB_STAT_00_CUR_BINMSTR                 (0xffL<<24)
2459 
2460 #define BNX2_DMA_ARB_STAT_01                0x00000d04
2461 #define BNX2_DMA_ARB_STAT_01_LPR_RPTR                    (0xfL<<0)
2462 #define BNX2_DMA_ARB_STAT_01_LPR_WPTR                    (0xfL<<4)
2463 #define BNX2_DMA_ARB_STAT_01_LPB_RPTR                    (0xfL<<8)
2464 #define BNX2_DMA_ARB_STAT_01_LPB_WPTR                    (0xfL<<12)
2465 #define BNX2_DMA_ARB_STAT_01_HPR_RPTR                    (0xfL<<16)
2466 #define BNX2_DMA_ARB_STAT_01_HPR_WPTR                    (0xfL<<20)
2467 #define BNX2_DMA_ARB_STAT_01_HPB_RPTR                    (0xfL<<24)
2468 #define BNX2_DMA_ARB_STAT_01_HPB_WPTR                    (0xfL<<28)
2469 
2470 #define BNX2_DMA_FUSE_CTRL0_CMD             0x00000f00
2471 #define BNX2_DMA_FUSE_CTRL0_CMD_PWRUP_DONE               (1L<<0)
2472 #define BNX2_DMA_FUSE_CTRL0_CMD_SHIFT_DONE               (1L<<1)
2473 #define BNX2_DMA_FUSE_CTRL0_CMD_SHIFT                    (1L<<2)
2474 #define BNX2_DMA_FUSE_CTRL0_CMD_LOAD                     (1L<<3)
2475 #define BNX2_DMA_FUSE_CTRL0_CMD_SEL                      (0xfL<<8)
2476 
2477 #define BNX2_DMA_FUSE_CTRL0_DATA            0x00000f04
2478 #define BNX2_DMA_FUSE_CTRL1_CMD             0x00000f08
2479 #define BNX2_DMA_FUSE_CTRL1_CMD_PWRUP_DONE               (1L<<0)
2480 #define BNX2_DMA_FUSE_CTRL1_CMD_SHIFT_DONE               (1L<<1)
2481 #define BNX2_DMA_FUSE_CTRL1_CMD_SHIFT                    (1L<<2)
2482 #define BNX2_DMA_FUSE_CTRL1_CMD_LOAD                     (1L<<3)
2483 #define BNX2_DMA_FUSE_CTRL1_CMD_SEL                      (0xfL<<8)
2484 
2485 #define BNX2_DMA_FUSE_CTRL1_DATA            0x00000f0c
2486 #define BNX2_DMA_FUSE_CTRL2_CMD             0x00000f10
2487 #define BNX2_DMA_FUSE_CTRL2_CMD_PWRUP_DONE               (1L<<0)
2488 #define BNX2_DMA_FUSE_CTRL2_CMD_SHIFT_DONE               (1L<<1)
2489 #define BNX2_DMA_FUSE_CTRL2_CMD_SHIFT                    (1L<<2)
2490 #define BNX2_DMA_FUSE_CTRL2_CMD_LOAD                     (1L<<3)
2491 #define BNX2_DMA_FUSE_CTRL2_CMD_SEL                      (0xfL<<8)
2492 
2493 #define BNX2_DMA_FUSE_CTRL2_DATA            0x00000f14
2494 
2495 
2496 /*
2497  *  context_reg definition
2498  *  offset: 0x1000
2499  */
2500 #define BNX2_CTX_COMMAND                0x00001000
2501 #define BNX2_CTX_COMMAND_ENABLED                         (1L<<0)
2502 #define BNX2_CTX_COMMAND_DISABLE_USAGE_CNT               (1L<<1)
2503 #define BNX2_CTX_COMMAND_DISABLE_PLRU                    (1L<<2)
2504 #define BNX2_CTX_COMMAND_DISABLE_COMBINE_READ            (1L<<3)
2505 #define BNX2_CTX_COMMAND_FLUSH_AHEAD                     (0x1fL<<8)
2506 #define BNX2_CTX_COMMAND_MEM_INIT                        (1L<<13)
2507 #define BNX2_CTX_COMMAND_PAGE_SIZE                       (0xfL<<16)
2508 #define BNX2_CTX_COMMAND_PAGE_SIZE_256                   (0L<<16)
2509 #define BNX2_CTX_COMMAND_PAGE_SIZE_512                   (1L<<16)
2510 #define BNX2_CTX_COMMAND_PAGE_SIZE_1K                    (2L<<16)
2511 #define BNX2_CTX_COMMAND_PAGE_SIZE_2K                    (3L<<16)
2512 #define BNX2_CTX_COMMAND_PAGE_SIZE_4K                    (4L<<16)
2513 #define BNX2_CTX_COMMAND_PAGE_SIZE_8K                    (5L<<16)
2514 #define BNX2_CTX_COMMAND_PAGE_SIZE_16K                   (6L<<16)
2515 #define BNX2_CTX_COMMAND_PAGE_SIZE_32K                   (7L<<16)
2516 #define BNX2_CTX_COMMAND_PAGE_SIZE_64K                   (8L<<16)
2517 #define BNX2_CTX_COMMAND_PAGE_SIZE_128K                  (9L<<16)
2518 #define BNX2_CTX_COMMAND_PAGE_SIZE_256K                  (10L<<16)
2519 #define BNX2_CTX_COMMAND_PAGE_SIZE_512K                  (11L<<16)
2520 #define BNX2_CTX_COMMAND_PAGE_SIZE_1M                    (12L<<16)
2521 
2522 #define BNX2_CTX_STATUS                 0x00001004
2523 #define BNX2_CTX_STATUS_LOCK_WAIT                        (1L<<0)
2524 #define BNX2_CTX_STATUS_READ_STAT                        (1L<<16)
2525 #define BNX2_CTX_STATUS_WRITE_STAT                       (1L<<17)
2526 #define BNX2_CTX_STATUS_ACC_STALL_STAT                   (1L<<18)
2527 #define BNX2_CTX_STATUS_LOCK_STALL_STAT                  (1L<<19)
2528 #define BNX2_CTX_STATUS_EXT_READ_STAT                    (1L<<20)
2529 #define BNX2_CTX_STATUS_EXT_WRITE_STAT                   (1L<<21)
2530 #define BNX2_CTX_STATUS_MISS_STAT                        (1L<<22)
2531 #define BNX2_CTX_STATUS_HIT_STAT                         (1L<<23)
2532 #define BNX2_CTX_STATUS_DEAD_LOCK                        (1L<<24)
2533 #define BNX2_CTX_STATUS_USAGE_CNT_ERR                    (1L<<25)
2534 #define BNX2_CTX_STATUS_INVALID_PAGE                     (1L<<26)
2535 
2536 #define BNX2_CTX_VIRT_ADDR              0x00001008
2537 #define BNX2_CTX_VIRT_ADDR_VIRT_ADDR                     (0x7fffL<<6)
2538 
2539 #define BNX2_CTX_PAGE_TBL               0x0000100c
2540 #define BNX2_CTX_PAGE_TBL_PAGE_TBL                       (0x3fffL<<6)
2541 
2542 #define BNX2_CTX_DATA_ADR               0x00001010
2543 #define BNX2_CTX_DATA_ADR_DATA_ADR                       (0x7ffffL<<2)
2544 
2545 #define BNX2_CTX_DATA                   0x00001014
2546 #define BNX2_CTX_LOCK                   0x00001018
2547 #define BNX2_CTX_LOCK_TYPE                               (0x7L<<0)
2548 #define BNX2_CTX_LOCK_TYPE_LOCK_TYPE_VOID                (0x0L<<0)
2549 #define BNX2_CTX_LOCK_TYPE_LOCK_TYPE_PROTOCOL            (0x1L<<0)
2550 #define BNX2_CTX_LOCK_TYPE_LOCK_TYPE_TX                  (0x2L<<0)
2551 #define BNX2_CTX_LOCK_TYPE_LOCK_TYPE_TIMER               (0x4L<<0)
2552 #define BNX2_CTX_LOCK_TYPE_LOCK_TYPE_COMPLETE            (0x7L<<0)
2553 #define BNX2_CTX_LOCK_TYPE_VOID_XI                       (0L<<0)
2554 #define BNX2_CTX_LOCK_TYPE_PROTOCOL_XI                   (1L<<0)
2555 #define BNX2_CTX_LOCK_TYPE_TX_XI                         (2L<<0)
2556 #define BNX2_CTX_LOCK_TYPE_TIMER_XI                      (4L<<0)
2557 #define BNX2_CTX_LOCK_TYPE_COMPLETE_XI                   (7L<<0)
2558 #define BNX2_CTX_LOCK_CID_VALUE                          (0x3fffL<<7)
2559 #define BNX2_CTX_LOCK_GRANTED                            (1L<<26)
2560 #define BNX2_CTX_LOCK_MODE                               (0x7L<<27)
2561 #define BNX2_CTX_LOCK_MODE_UNLOCK                        (0x0L<<27)
2562 #define BNX2_CTX_LOCK_MODE_IMMEDIATE                     (0x1L<<27)
2563 #define BNX2_CTX_LOCK_MODE_SURE                          (0x2L<<27)
2564 #define BNX2_CTX_LOCK_STATUS                             (1L<<30)
2565 #define BNX2_CTX_LOCK_REQ                                (1L<<31)
2566 
2567 #define BNX2_CTX_CTX_CTRL               0x0000101c
2568 #define BNX2_CTX_CTX_CTRL_CTX_ADDR                       (0x7ffffL<<2)
2569 #define BNX2_CTX_CTX_CTRL_MOD_USAGE_CNT                  (0x3L<<21)
2570 #define BNX2_CTX_CTX_CTRL_NO_RAM_ACC                     (1L<<23)
2571 #define BNX2_CTX_CTX_CTRL_PREFETCH_SIZE                  (0x3L<<24)
2572 #define BNX2_CTX_CTX_CTRL_ATTR                           (1L<<26)
2573 #define BNX2_CTX_CTX_CTRL_WRITE_REQ                      (1L<<30)
2574 #define BNX2_CTX_CTX_CTRL_READ_REQ                       (1L<<31)
2575 
2576 #define BNX2_CTX_CTX_DATA               0x00001020
2577 #define BNX2_CTX_ACCESS_STATUS              0x00001040
2578 #define BNX2_CTX_ACCESS_STATUS_MASTERENCODED             (0xfL<<0)
2579 #define BNX2_CTX_ACCESS_STATUS_ACCESSMEMORYSM            (0x3L<<10)
2580 #define BNX2_CTX_ACCESS_STATUS_PAGETABLEINITSM           (0x3L<<12)
2581 #define BNX2_CTX_ACCESS_STATUS_ACCESSMEMORYINITSM        (0x3L<<14)
2582 #define BNX2_CTX_ACCESS_STATUS_QUALIFIED_REQUEST         (0x7ffL<<17)
2583 #define BNX2_CTX_ACCESS_STATUS_CAMMASTERENCODED_XI       (0x1fL<<0)
2584 #define BNX2_CTX_ACCESS_STATUS_CACHEMASTERENCODED_XI     (0x1fL<<5)
2585 #define BNX2_CTX_ACCESS_STATUS_REQUEST_XI                (0x3fffffL<<10)
2586 
2587 #define BNX2_CTX_DBG_LOCK_STATUS            0x00001044
2588 #define BNX2_CTX_DBG_LOCK_STATUS_SM                      (0x3ffL<<0)
2589 #define BNX2_CTX_DBG_LOCK_STATUS_MATCH                   (0x3ffL<<22)
2590 
2591 #define BNX2_CTX_CACHE_CTRL_STATUS          0x00001048
2592 #define BNX2_CTX_CACHE_CTRL_STATUS_RFIFO_OVERFLOW        (1L<<0)
2593 #define BNX2_CTX_CACHE_CTRL_STATUS_INVALID_READ_COMP     (1L<<1)
2594 #define BNX2_CTX_CACHE_CTRL_STATUS_FLUSH_START           (1L<<6)
2595 #define BNX2_CTX_CACHE_CTRL_STATUS_FREE_ENTRY_CNT        (0x3fL<<7)
2596 #define BNX2_CTX_CACHE_CTRL_STATUS_CACHE_ENTRY_NEEDED    (0x3fL<<13)
2597 #define BNX2_CTX_CACHE_CTRL_STATUS_RD_CHAN0_ACTIVE       (1L<<19)
2598 #define BNX2_CTX_CACHE_CTRL_STATUS_RD_CHAN1_ACTIVE       (1L<<20)
2599 #define BNX2_CTX_CACHE_CTRL_STATUS_RD_CHAN2_ACTIVE       (1L<<21)
2600 #define BNX2_CTX_CACHE_CTRL_STATUS_RD_CHAN3_ACTIVE       (1L<<22)
2601 #define BNX2_CTX_CACHE_CTRL_STATUS_RD_CHAN4_ACTIVE       (1L<<23)
2602 #define BNX2_CTX_CACHE_CTRL_STATUS_RD_CHAN5_ACTIVE       (1L<<24)
2603 #define BNX2_CTX_CACHE_CTRL_STATUS_RD_CHAN6_ACTIVE       (1L<<25)
2604 #define BNX2_CTX_CACHE_CTRL_STATUS_RD_CHAN7_ACTIVE       (1L<<26)
2605 #define BNX2_CTX_CACHE_CTRL_STATUS_RD_CHAN8_ACTIVE       (1L<<27)
2606 #define BNX2_CTX_CACHE_CTRL_STATUS_RD_CHAN9_ACTIVE       (1L<<28)
2607 #define BNX2_CTX_CACHE_CTRL_STATUS_RD_CHAN10_ACTIVE      (1L<<29)
2608 
2609 #define BNX2_CTX_CACHE_CTRL_SM_STATUS           0x0000104c
2610 #define BNX2_CTX_CACHE_CTRL_SM_STATUS_CS_DWC             (0x7L<<0)
2611 #define BNX2_CTX_CACHE_CTRL_SM_STATUS_CS_WFIFOC          (0x7L<<3)
2612 #define BNX2_CTX_CACHE_CTRL_SM_STATUS_CS_RTAGC           (0x7L<<6)
2613 #define BNX2_CTX_CACHE_CTRL_SM_STATUS_CS_RFIFOC          (0x7L<<9)
2614 #define BNX2_CTX_CACHE_CTRL_SM_STATUS_INVALID_BLK_ADDR   (0x7fffL<<16)
2615 
2616 #define BNX2_CTX_CACHE_STATUS               0x00001050
2617 #define BNX2_CTX_CACHE_STATUS_HELD_ENTRIES               (0x3ffL<<0)
2618 #define BNX2_CTX_CACHE_STATUS_MAX_HELD_ENTRIES           (0x3ffL<<16)
2619 
2620 #define BNX2_CTX_DMA_STATUS             0x00001054
2621 #define BNX2_CTX_DMA_STATUS_RD_CHAN0_STATUS              (0x3L<<0)
2622 #define BNX2_CTX_DMA_STATUS_RD_CHAN1_STATUS              (0x3L<<2)
2623 #define BNX2_CTX_DMA_STATUS_RD_CHAN2_STATUS              (0x3L<<4)
2624 #define BNX2_CTX_DMA_STATUS_RD_CHAN3_STATUS              (0x3L<<6)
2625 #define BNX2_CTX_DMA_STATUS_RD_CHAN4_STATUS              (0x3L<<8)
2626 #define BNX2_CTX_DMA_STATUS_RD_CHAN5_STATUS              (0x3L<<10)
2627 #define BNX2_CTX_DMA_STATUS_RD_CHAN6_STATUS              (0x3L<<12)
2628 #define BNX2_CTX_DMA_STATUS_RD_CHAN7_STATUS              (0x3L<<14)
2629 #define BNX2_CTX_DMA_STATUS_RD_CHAN8_STATUS              (0x3L<<16)
2630 #define BNX2_CTX_DMA_STATUS_RD_CHAN9_STATUS              (0x3L<<18)
2631 #define BNX2_CTX_DMA_STATUS_RD_CHAN10_STATUS             (0x3L<<20)
2632 
2633 #define BNX2_CTX_REP_STATUS             0x00001058
2634 #define BNX2_CTX_REP_STATUS_ERROR_ENTRY                  (0x3ffL<<0)
2635 #define BNX2_CTX_REP_STATUS_ERROR_CLIENT_ID              (0x1fL<<10)
2636 #define BNX2_CTX_REP_STATUS_USAGE_CNT_MAX_ERR            (1L<<16)
2637 #define BNX2_CTX_REP_STATUS_USAGE_CNT_MIN_ERR            (1L<<17)
2638 #define BNX2_CTX_REP_STATUS_USAGE_CNT_MISS_ERR           (1L<<18)
2639 
2640 #define BNX2_CTX_CKSUM_ERROR_STATUS         0x0000105c
2641 #define BNX2_CTX_CKSUM_ERROR_STATUS_CALCULATED           (0xffffL<<0)
2642 #define BNX2_CTX_CKSUM_ERROR_STATUS_EXPECTED             (0xffffL<<16)
2643 
2644 #define BNX2_CTX_CHNL_LOCK_STATUS_0         0x00001080
2645 #define BNX2_CTX_CHNL_LOCK_STATUS_0_CID                  (0x3fffL<<0)
2646 #define BNX2_CTX_CHNL_LOCK_STATUS_0_TYPE                 (0x3L<<14)
2647 #define BNX2_CTX_CHNL_LOCK_STATUS_0_MODE                 (1L<<16)
2648 #define BNX2_CTX_CHNL_LOCK_STATUS_0_MODE_XI              (1L<<14)
2649 #define BNX2_CTX_CHNL_LOCK_STATUS_0_TYPE_XI              (0x7L<<15)
2650 
2651 #define BNX2_CTX_CHNL_LOCK_STATUS_1         0x00001084
2652 #define BNX2_CTX_CHNL_LOCK_STATUS_2         0x00001088
2653 #define BNX2_CTX_CHNL_LOCK_STATUS_3         0x0000108c
2654 #define BNX2_CTX_CHNL_LOCK_STATUS_4         0x00001090
2655 #define BNX2_CTX_CHNL_LOCK_STATUS_5         0x00001094
2656 #define BNX2_CTX_CHNL_LOCK_STATUS_6         0x00001098
2657 #define BNX2_CTX_CHNL_LOCK_STATUS_7         0x0000109c
2658 #define BNX2_CTX_CHNL_LOCK_STATUS_8         0x000010a0
2659 #define BNX2_CTX_CHNL_LOCK_STATUS_9         0x000010a4
2660 
2661 #define BNX2_CTX_CACHE_DATA             0x000010c4
2662 #define BNX2_CTX_HOST_PAGE_TBL_CTRL         0x000010c8
2663 #define BNX2_CTX_HOST_PAGE_TBL_CTRL_PAGE_TBL_ADDR        (0x1ffL<<0)
2664 #define BNX2_CTX_HOST_PAGE_TBL_CTRL_WRITE_REQ            (1L<<30)
2665 #define BNX2_CTX_HOST_PAGE_TBL_CTRL_READ_REQ             (1L<<31)
2666 
2667 #define BNX2_CTX_HOST_PAGE_TBL_DATA0            0x000010cc
2668 #define BNX2_CTX_HOST_PAGE_TBL_DATA0_VALID               (1L<<0)
2669 #define BNX2_CTX_HOST_PAGE_TBL_DATA0_VALUE               (0xffffffL<<8)
2670 
2671 #define BNX2_CTX_HOST_PAGE_TBL_DATA1            0x000010d0
2672 #define BNX2_CTX_CAM_CTRL               0x000010d4
2673 #define BNX2_CTX_CAM_CTRL_CAM_ADDR                       (0x3ffL<<0)
2674 #define BNX2_CTX_CAM_CTRL_RESET                          (1L<<27)
2675 #define BNX2_CTX_CAM_CTRL_INVALIDATE                     (1L<<28)
2676 #define BNX2_CTX_CAM_CTRL_SEARCH                         (1L<<29)
2677 #define BNX2_CTX_CAM_CTRL_WRITE_REQ                      (1L<<30)
2678 #define BNX2_CTX_CAM_CTRL_READ_REQ                       (1L<<31)
2679 
2680 
2681 /*
2682  *  emac_reg definition
2683  *  offset: 0x1400
2684  */
2685 #define BNX2_EMAC_MODE                  0x00001400
2686 #define BNX2_EMAC_MODE_RESET                             (1L<<0)
2687 #define BNX2_EMAC_MODE_HALF_DUPLEX                       (1L<<1)
2688 #define BNX2_EMAC_MODE_PORT                              (0x3L<<2)
2689 #define BNX2_EMAC_MODE_PORT_NONE                         (0L<<2)
2690 #define BNX2_EMAC_MODE_PORT_MII                          (1L<<2)
2691 #define BNX2_EMAC_MODE_PORT_GMII                         (2L<<2)
2692 #define BNX2_EMAC_MODE_PORT_MII_10M                      (3L<<2)
2693 #define BNX2_EMAC_MODE_MAC_LOOP                          (1L<<4)
2694 #define BNX2_EMAC_MODE_25G_MODE                          (1L<<5)
2695 #define BNX2_EMAC_MODE_TAGGED_MAC_CTL                    (1L<<7)
2696 #define BNX2_EMAC_MODE_TX_BURST                          (1L<<8)
2697 #define BNX2_EMAC_MODE_MAX_DEFER_DROP_ENA                (1L<<9)
2698 #define BNX2_EMAC_MODE_EXT_LINK_POL                      (1L<<10)
2699 #define BNX2_EMAC_MODE_FORCE_LINK                        (1L<<11)
2700 #define BNX2_EMAC_MODE_SERDES_MODE                       (1L<<12)
2701 #define BNX2_EMAC_MODE_BOND_OVRD                         (1L<<13)
2702 #define BNX2_EMAC_MODE_MPKT                              (1L<<18)
2703 #define BNX2_EMAC_MODE_MPKT_RCVD                         (1L<<19)
2704 #define BNX2_EMAC_MODE_ACPI_RCVD                         (1L<<20)
2705 
2706 #define BNX2_EMAC_STATUS                0x00001404
2707 #define BNX2_EMAC_STATUS_LINK                            (1L<<11)
2708 #define BNX2_EMAC_STATUS_LINK_CHANGE                     (1L<<12)
2709 #define BNX2_EMAC_STATUS_SERDES_AUTONEG_COMPLETE         (1L<<13)
2710 #define BNX2_EMAC_STATUS_SERDES_AUTONEG_CHANGE           (1L<<14)
2711 #define BNX2_EMAC_STATUS_SERDES_NXT_PG_CHANGE            (1L<<16)
2712 #define BNX2_EMAC_STATUS_SERDES_RX_CONFIG_IS_0           (1L<<17)
2713 #define BNX2_EMAC_STATUS_SERDES_RX_CONFIG_IS_0_CHANGE    (1L<<18)
2714 #define BNX2_EMAC_STATUS_MI_COMPLETE                     (1L<<22)
2715 #define BNX2_EMAC_STATUS_MI_INT                          (1L<<23)
2716 #define BNX2_EMAC_STATUS_AP_ERROR                        (1L<<24)
2717 #define BNX2_EMAC_STATUS_PARITY_ERROR_STATE              (1L<<31)
2718 
2719 #define BNX2_EMAC_ATTENTION_ENA             0x00001408
2720 #define BNX2_EMAC_ATTENTION_ENA_LINK                     (1L<<11)
2721 #define BNX2_EMAC_ATTENTION_ENA_AUTONEG_CHANGE           (1L<<14)
2722 #define BNX2_EMAC_ATTENTION_ENA_NXT_PG_CHANGE            (1L<<16)
2723 #define BNX2_EMAC_ATTENTION_ENA_SERDES_RX_CONFIG_IS_0_CHANGE     (1L<<18)
2724 #define BNX2_EMAC_ATTENTION_ENA_MI_COMPLETE              (1L<<22)
2725 #define BNX2_EMAC_ATTENTION_ENA_MI_INT                   (1L<<23)
2726 #define BNX2_EMAC_ATTENTION_ENA_AP_ERROR                 (1L<<24)
2727 
2728 #define BNX2_EMAC_LED                   0x0000140c
2729 #define BNX2_EMAC_LED_OVERRIDE                           (1L<<0)
2730 #define BNX2_EMAC_LED_1000MB_OVERRIDE                    (1L<<1)
2731 #define BNX2_EMAC_LED_100MB_OVERRIDE                     (1L<<2)
2732 #define BNX2_EMAC_LED_10MB_OVERRIDE                      (1L<<3)
2733 #define BNX2_EMAC_LED_TRAFFIC_OVERRIDE                   (1L<<4)
2734 #define BNX2_EMAC_LED_BLNK_TRAFFIC                       (1L<<5)
2735 #define BNX2_EMAC_LED_TRAFFIC                            (1L<<6)
2736 #define BNX2_EMAC_LED_1000MB                             (1L<<7)
2737 #define BNX2_EMAC_LED_100MB                              (1L<<8)
2738 #define BNX2_EMAC_LED_10MB                               (1L<<9)
2739 #define BNX2_EMAC_LED_TRAFFIC_STAT                       (1L<<10)
2740 #define BNX2_EMAC_LED_2500MB                             (1L<<11)
2741 #define BNX2_EMAC_LED_2500MB_OVERRIDE                    (1L<<12)
2742 #define BNX2_EMAC_LED_ACTIVITY_SEL                       (0x3L<<17)
2743 #define BNX2_EMAC_LED_ACTIVITY_SEL_0                     (0L<<17)
2744 #define BNX2_EMAC_LED_ACTIVITY_SEL_1                     (1L<<17)
2745 #define BNX2_EMAC_LED_ACTIVITY_SEL_2                     (2L<<17)
2746 #define BNX2_EMAC_LED_ACTIVITY_SEL_3                     (3L<<17)
2747 #define BNX2_EMAC_LED_BLNK_RATE                          (0xfffL<<19)
2748 #define BNX2_EMAC_LED_BLNK_RATE_ENA                      (1L<<31)
2749 
2750 #define BNX2_EMAC_MAC_MATCH0                0x00001410
2751 #define BNX2_EMAC_MAC_MATCH1                0x00001414
2752 #define BNX2_EMAC_MAC_MATCH2                0x00001418
2753 #define BNX2_EMAC_MAC_MATCH3                0x0000141c
2754 #define BNX2_EMAC_MAC_MATCH4                0x00001420
2755 #define BNX2_EMAC_MAC_MATCH5                0x00001424
2756 #define BNX2_EMAC_MAC_MATCH6                0x00001428
2757 #define BNX2_EMAC_MAC_MATCH7                0x0000142c
2758 #define BNX2_EMAC_MAC_MATCH8                0x00001430
2759 #define BNX2_EMAC_MAC_MATCH9                0x00001434
2760 #define BNX2_EMAC_MAC_MATCH10               0x00001438
2761 #define BNX2_EMAC_MAC_MATCH11               0x0000143c
2762 #define BNX2_EMAC_MAC_MATCH12               0x00001440
2763 #define BNX2_EMAC_MAC_MATCH13               0x00001444
2764 #define BNX2_EMAC_MAC_MATCH14               0x00001448
2765 #define BNX2_EMAC_MAC_MATCH15               0x0000144c
2766 #define BNX2_EMAC_MAC_MATCH16               0x00001450
2767 #define BNX2_EMAC_MAC_MATCH17               0x00001454
2768 #define BNX2_EMAC_MAC_MATCH18               0x00001458
2769 #define BNX2_EMAC_MAC_MATCH19               0x0000145c
2770 #define BNX2_EMAC_MAC_MATCH20               0x00001460
2771 #define BNX2_EMAC_MAC_MATCH21               0x00001464
2772 #define BNX2_EMAC_MAC_MATCH22               0x00001468
2773 #define BNX2_EMAC_MAC_MATCH23               0x0000146c
2774 #define BNX2_EMAC_MAC_MATCH24               0x00001470
2775 #define BNX2_EMAC_MAC_MATCH25               0x00001474
2776 #define BNX2_EMAC_MAC_MATCH26               0x00001478
2777 #define BNX2_EMAC_MAC_MATCH27               0x0000147c
2778 #define BNX2_EMAC_MAC_MATCH28               0x00001480
2779 #define BNX2_EMAC_MAC_MATCH29               0x00001484
2780 #define BNX2_EMAC_MAC_MATCH30               0x00001488
2781 #define BNX2_EMAC_MAC_MATCH31               0x0000148c
2782 #define BNX2_EMAC_BACKOFF_SEED              0x00001498
2783 #define BNX2_EMAC_BACKOFF_SEED_EMAC_BACKOFF_SEED         (0x3ffL<<0)
2784 
2785 #define BNX2_EMAC_RX_MTU_SIZE               0x0000149c
2786 #define BNX2_EMAC_RX_MTU_SIZE_MTU_SIZE                   (0xffffL<<0)
2787 #define BNX2_EMAC_RX_MTU_SIZE_JUMBO_ENA                  (1L<<31)
2788 
2789 #define BNX2_EMAC_SERDES_CNTL               0x000014a4
2790 #define BNX2_EMAC_SERDES_CNTL_RXR                        (0x7L<<0)
2791 #define BNX2_EMAC_SERDES_CNTL_RXG                        (0x3L<<3)
2792 #define BNX2_EMAC_SERDES_CNTL_RXCKSEL                    (1L<<6)
2793 #define BNX2_EMAC_SERDES_CNTL_TXBIAS                     (0x7L<<7)
2794 #define BNX2_EMAC_SERDES_CNTL_BGMAX                      (1L<<10)
2795 #define BNX2_EMAC_SERDES_CNTL_BGMIN                      (1L<<11)
2796 #define BNX2_EMAC_SERDES_CNTL_TXMODE                     (1L<<12)
2797 #define BNX2_EMAC_SERDES_CNTL_TXEDGE                     (1L<<13)
2798 #define BNX2_EMAC_SERDES_CNTL_SERDES_MODE                (1L<<14)
2799 #define BNX2_EMAC_SERDES_CNTL_PLLTEST                    (1L<<15)
2800 #define BNX2_EMAC_SERDES_CNTL_CDET_EN                    (1L<<16)
2801 #define BNX2_EMAC_SERDES_CNTL_TBI_LBK                    (1L<<17)
2802 #define BNX2_EMAC_SERDES_CNTL_REMOTE_LBK                 (1L<<18)
2803 #define BNX2_EMAC_SERDES_CNTL_REV_PHASE                  (1L<<19)
2804 #define BNX2_EMAC_SERDES_CNTL_REGCTL12                   (0x3L<<20)
2805 #define BNX2_EMAC_SERDES_CNTL_REGCTL25                   (0x3L<<22)
2806 
2807 #define BNX2_EMAC_SERDES_STATUS             0x000014a8
2808 #define BNX2_EMAC_SERDES_STATUS_RX_STAT                  (0xffL<<0)
2809 #define BNX2_EMAC_SERDES_STATUS_COMMA_DET                (1L<<8)
2810 
2811 #define BNX2_EMAC_MDIO_COMM             0x000014ac
2812 #define BNX2_EMAC_MDIO_COMM_DATA                         (0xffffL<<0)
2813 #define BNX2_EMAC_MDIO_COMM_REG_ADDR                     (0x1fL<<16)
2814 #define BNX2_EMAC_MDIO_COMM_PHY_ADDR                     (0x1fL<<21)
2815 #define BNX2_EMAC_MDIO_COMM_COMMAND                      (0x3L<<26)
2816 #define BNX2_EMAC_MDIO_COMM_COMMAND_UNDEFINED_0          (0L<<26)
2817 #define BNX2_EMAC_MDIO_COMM_COMMAND_ADDRESS              (0L<<26)
2818 #define BNX2_EMAC_MDIO_COMM_COMMAND_WRITE                (1L<<26)
2819 #define BNX2_EMAC_MDIO_COMM_COMMAND_READ                 (2L<<26)
2820 #define BNX2_EMAC_MDIO_COMM_COMMAND_WRITE_22_XI          (1L<<26)
2821 #define BNX2_EMAC_MDIO_COMM_COMMAND_WRITE_45_XI          (1L<<26)
2822 #define BNX2_EMAC_MDIO_COMM_COMMAND_READ_22_XI           (2L<<26)
2823 #define BNX2_EMAC_MDIO_COMM_COMMAND_READ_INC_45_XI       (2L<<26)
2824 #define BNX2_EMAC_MDIO_COMM_COMMAND_UNDEFINED_3          (3L<<26)
2825 #define BNX2_EMAC_MDIO_COMM_COMMAND_READ_45              (3L<<26)
2826 #define BNX2_EMAC_MDIO_COMM_FAIL                         (1L<<28)
2827 #define BNX2_EMAC_MDIO_COMM_START_BUSY                   (1L<<29)
2828 #define BNX2_EMAC_MDIO_COMM_DISEXT                       (1L<<30)
2829 
2830 #define BNX2_EMAC_MDIO_STATUS               0x000014b0
2831 #define BNX2_EMAC_MDIO_STATUS_LINK                       (1L<<0)
2832 #define BNX2_EMAC_MDIO_STATUS_10MB                       (1L<<1)
2833 
2834 #define BNX2_EMAC_MDIO_MODE             0x000014b4
2835 #define BNX2_EMAC_MDIO_MODE_SHORT_PREAMBLE               (1L<<1)
2836 #define BNX2_EMAC_MDIO_MODE_AUTO_POLL                    (1L<<4)
2837 #define BNX2_EMAC_MDIO_MODE_BIT_BANG                     (1L<<8)
2838 #define BNX2_EMAC_MDIO_MODE_MDIO                         (1L<<9)
2839 #define BNX2_EMAC_MDIO_MODE_MDIO_OE                      (1L<<10)
2840 #define BNX2_EMAC_MDIO_MODE_MDC                          (1L<<11)
2841 #define BNX2_EMAC_MDIO_MODE_MDINT                        (1L<<12)
2842 #define BNX2_EMAC_MDIO_MODE_EXT_MDINT                    (1L<<13)
2843 #define BNX2_EMAC_MDIO_MODE_CLOCK_CNT                    (0x1fL<<16)
2844 #define BNX2_EMAC_MDIO_MODE_CLOCK_CNT_XI                 (0x3fL<<16)
2845 #define BNX2_EMAC_MDIO_MODE_CLAUSE_45_XI                 (1L<<31)
2846 
2847 #define BNX2_EMAC_MDIO_AUTO_STATUS          0x000014b8
2848 #define BNX2_EMAC_MDIO_AUTO_STATUS_AUTO_ERR              (1L<<0)
2849 
2850 #define BNX2_EMAC_TX_MODE               0x000014bc
2851 #define BNX2_EMAC_TX_MODE_RESET                          (1L<<0)
2852 #define BNX2_EMAC_TX_MODE_CS16_TEST                      (1L<<2)
2853 #define BNX2_EMAC_TX_MODE_EXT_PAUSE_EN                   (1L<<3)
2854 #define BNX2_EMAC_TX_MODE_FLOW_EN                        (1L<<4)
2855 #define BNX2_EMAC_TX_MODE_BIG_BACKOFF                    (1L<<5)
2856 #define BNX2_EMAC_TX_MODE_LONG_PAUSE                     (1L<<6)
2857 #define BNX2_EMAC_TX_MODE_LINK_AWARE                     (1L<<7)
2858 
2859 #define BNX2_EMAC_TX_STATUS             0x000014c0
2860 #define BNX2_EMAC_TX_STATUS_XOFFED                       (1L<<0)
2861 #define BNX2_EMAC_TX_STATUS_XOFF_SENT                    (1L<<1)
2862 #define BNX2_EMAC_TX_STATUS_XON_SENT                     (1L<<2)
2863 #define BNX2_EMAC_TX_STATUS_LINK_UP                      (1L<<3)
2864 #define BNX2_EMAC_TX_STATUS_UNDERRUN                     (1L<<4)
2865 #define BNX2_EMAC_TX_STATUS_CS16_ERROR                   (1L<<5)
2866 
2867 #define BNX2_EMAC_TX_LENGTHS                0x000014c4
2868 #define BNX2_EMAC_TX_LENGTHS_SLOT                        (0xffL<<0)
2869 #define BNX2_EMAC_TX_LENGTHS_IPG                         (0xfL<<8)
2870 #define BNX2_EMAC_TX_LENGTHS_IPG_CRS                     (0x3L<<12)
2871 
2872 #define BNX2_EMAC_RX_MODE               0x000014c8
2873 #define BNX2_EMAC_RX_MODE_RESET                          (1L<<0)
2874 #define BNX2_EMAC_RX_MODE_FLOW_EN                        (1L<<2)
2875 #define BNX2_EMAC_RX_MODE_KEEP_MAC_CONTROL               (1L<<3)
2876 #define BNX2_EMAC_RX_MODE_KEEP_PAUSE                     (1L<<4)
2877 #define BNX2_EMAC_RX_MODE_ACCEPT_OVERSIZE                (1L<<5)
2878 #define BNX2_EMAC_RX_MODE_ACCEPT_RUNTS                   (1L<<6)
2879 #define BNX2_EMAC_RX_MODE_LLC_CHK                        (1L<<7)
2880 #define BNX2_EMAC_RX_MODE_PROMISCUOUS                    (1L<<8)
2881 #define BNX2_EMAC_RX_MODE_NO_CRC_CHK                     (1L<<9)
2882 #define BNX2_EMAC_RX_MODE_KEEP_VLAN_TAG                  (1L<<10)
2883 #define BNX2_EMAC_RX_MODE_FILT_BROADCAST                 (1L<<11)
2884 #define BNX2_EMAC_RX_MODE_SORT_MODE                      (1L<<12)
2885 
2886 #define BNX2_EMAC_RX_STATUS             0x000014cc
2887 #define BNX2_EMAC_RX_STATUS_FFED                         (1L<<0)
2888 #define BNX2_EMAC_RX_STATUS_FF_RECEIVED                  (1L<<1)
2889 #define BNX2_EMAC_RX_STATUS_N_RECEIVED                   (1L<<2)
2890 
2891 #define BNX2_EMAC_MULTICAST_HASH0           0x000014d0
2892 #define BNX2_EMAC_MULTICAST_HASH1           0x000014d4
2893 #define BNX2_EMAC_MULTICAST_HASH2           0x000014d8
2894 #define BNX2_EMAC_MULTICAST_HASH3           0x000014dc
2895 #define BNX2_EMAC_MULTICAST_HASH4           0x000014e0
2896 #define BNX2_EMAC_MULTICAST_HASH5           0x000014e4
2897 #define BNX2_EMAC_MULTICAST_HASH6           0x000014e8
2898 #define BNX2_EMAC_MULTICAST_HASH7           0x000014ec
2899 #define BNX2_EMAC_CKSUM_ERROR_STATUS            0x000014f0
2900 #define BNX2_EMAC_CKSUM_ERROR_STATUS_CALCULATED          (0xffffL<<0)
2901 #define BNX2_EMAC_CKSUM_ERROR_STATUS_EXPECTED            (0xffffL<<16)
2902 
2903 #define BNX2_EMAC_RX_STAT_IFHCINOCTETS          0x00001500
2904 #define BNX2_EMAC_RX_STAT_IFHCINBADOCTETS       0x00001504
2905 #define BNX2_EMAC_RX_STAT_ETHERSTATSFRAGMENTS       0x00001508
2906 #define BNX2_EMAC_RX_STAT_IFHCINUCASTPKTS       0x0000150c
2907 #define BNX2_EMAC_RX_STAT_IFHCINMULTICASTPKTS       0x00001510
2908 #define BNX2_EMAC_RX_STAT_IFHCINBROADCASTPKTS       0x00001514
2909 #define BNX2_EMAC_RX_STAT_DOT3STATSFCSERRORS        0x00001518
2910 #define BNX2_EMAC_RX_STAT_DOT3STATSALIGNMENTERRORS  0x0000151c
2911 #define BNX2_EMAC_RX_STAT_DOT3STATSCARRIERSENSEERRORS   0x00001520
2912 #define BNX2_EMAC_RX_STAT_XONPAUSEFRAMESRECEIVED    0x00001524
2913 #define BNX2_EMAC_RX_STAT_XOFFPAUSEFRAMESRECEIVED   0x00001528
2914 #define BNX2_EMAC_RX_STAT_MACCONTROLFRAMESRECEIVED  0x0000152c
2915 #define BNX2_EMAC_RX_STAT_XOFFSTATEENTERED      0x00001530
2916 #define BNX2_EMAC_RX_STAT_DOT3STATSFRAMESTOOLONG    0x00001534
2917 #define BNX2_EMAC_RX_STAT_ETHERSTATSJABBERS     0x00001538
2918 #define BNX2_EMAC_RX_STAT_ETHERSTATSUNDERSIZEPKTS   0x0000153c
2919 #define BNX2_EMAC_RX_STAT_ETHERSTATSPKTS64OCTETS    0x00001540
2920 #define BNX2_EMAC_RX_STAT_ETHERSTATSPKTS65OCTETSTO127OCTETS 0x00001544
2921 #define BNX2_EMAC_RX_STAT_ETHERSTATSPKTS128OCTETSTO255OCTETS    0x00001548
2922 #define BNX2_EMAC_RX_STAT_ETHERSTATSPKTS256OCTETSTO511OCTETS    0x0000154c
2923 #define BNX2_EMAC_RX_STAT_ETHERSTATSPKTS512OCTETSTO1023OCTETS   0x00001550
2924 #define BNX2_EMAC_RX_STAT_ETHERSTATSPKTS1024OCTETSTO1522OCTETS  0x00001554
2925 #define BNX2_EMAC_RX_STAT_ETHERSTATSPKTSOVER1522OCTETS  0x00001558
2926 #define BNX2_EMAC_RXMAC_DEBUG0              0x0000155c
2927 #define BNX2_EMAC_RXMAC_DEBUG1              0x00001560
2928 #define BNX2_EMAC_RXMAC_DEBUG1_LENGTH_NE_BYTE_COUNT      (1L<<0)
2929 #define BNX2_EMAC_RXMAC_DEBUG1_LENGTH_OUT_RANGE          (1L<<1)
2930 #define BNX2_EMAC_RXMAC_DEBUG1_BAD_CRC                   (1L<<2)
2931 #define BNX2_EMAC_RXMAC_DEBUG1_RX_ERROR                  (1L<<3)
2932 #define BNX2_EMAC_RXMAC_DEBUG1_ALIGN_ERROR               (1L<<4)
2933 #define BNX2_EMAC_RXMAC_DEBUG1_LAST_DATA                 (1L<<5)
2934 #define BNX2_EMAC_RXMAC_DEBUG1_ODD_BYTE_START            (1L<<6)
2935 #define BNX2_EMAC_RXMAC_DEBUG1_BYTE_COUNT                (0xffffL<<7)
2936 #define BNX2_EMAC_RXMAC_DEBUG1_SLOT_TIME                 (0xffL<<23)
2937 
2938 #define BNX2_EMAC_RXMAC_DEBUG2              0x00001564
2939 #define BNX2_EMAC_RXMAC_DEBUG2_SM_STATE                  (0x7L<<0)
2940 #define BNX2_EMAC_RXMAC_DEBUG2_SM_STATE_IDLE             (0x0L<<0)
2941 #define BNX2_EMAC_RXMAC_DEBUG2_SM_STATE_SFD              (0x1L<<0)
2942 #define BNX2_EMAC_RXMAC_DEBUG2_SM_STATE_DATA             (0x2L<<0)
2943 #define BNX2_EMAC_RXMAC_DEBUG2_SM_STATE_SKEEP            (0x3L<<0)
2944 #define BNX2_EMAC_RXMAC_DEBUG2_SM_STATE_EXT              (0x4L<<0)
2945 #define BNX2_EMAC_RXMAC_DEBUG2_SM_STATE_DROP             (0x5L<<0)
2946 #define BNX2_EMAC_RXMAC_DEBUG2_SM_STATE_SDROP            (0x6L<<0)
2947 #define BNX2_EMAC_RXMAC_DEBUG2_SM_STATE_FC               (0x7L<<0)
2948 #define BNX2_EMAC_RXMAC_DEBUG2_IDI_STATE                 (0xfL<<3)
2949 #define BNX2_EMAC_RXMAC_DEBUG2_IDI_STATE_IDLE            (0x0L<<3)
2950 #define BNX2_EMAC_RXMAC_DEBUG2_IDI_STATE_DATA0           (0x1L<<3)
2951 #define BNX2_EMAC_RXMAC_DEBUG2_IDI_STATE_DATA1           (0x2L<<3)
2952 #define BNX2_EMAC_RXMAC_DEBUG2_IDI_STATE_DATA2           (0x3L<<3)
2953 #define BNX2_EMAC_RXMAC_DEBUG2_IDI_STATE_DATA3           (0x4L<<3)
2954 #define BNX2_EMAC_RXMAC_DEBUG2_IDI_STATE_ABORT           (0x5L<<3)
2955 #define BNX2_EMAC_RXMAC_DEBUG2_IDI_STATE_WAIT            (0x6L<<3)
2956 #define BNX2_EMAC_RXMAC_DEBUG2_IDI_STATE_STATUS          (0x7L<<3)
2957 #define BNX2_EMAC_RXMAC_DEBUG2_IDI_STATE_LAST            (0x8L<<3)
2958 #define BNX2_EMAC_RXMAC_DEBUG2_BYTE_IN                   (0xffL<<7)
2959 #define BNX2_EMAC_RXMAC_DEBUG2_FALSEC                    (1L<<15)
2960 #define BNX2_EMAC_RXMAC_DEBUG2_TAGGED                    (1L<<16)
2961 #define BNX2_EMAC_RXMAC_DEBUG2_PAUSE_STATE               (1L<<18)
2962 #define BNX2_EMAC_RXMAC_DEBUG2_PAUSE_STATE_IDLE          (0L<<18)
2963 #define BNX2_EMAC_RXMAC_DEBUG2_PAUSE_STATE_PAUSED        (1L<<18)
2964 #define BNX2_EMAC_RXMAC_DEBUG2_SE_COUNTER                (0xfL<<19)
2965 #define BNX2_EMAC_RXMAC_DEBUG2_QUANTA                    (0x1fL<<23)
2966 
2967 #define BNX2_EMAC_RXMAC_DEBUG3              0x00001568
2968 #define BNX2_EMAC_RXMAC_DEBUG3_PAUSE_CTR                 (0xffffL<<0)
2969 #define BNX2_EMAC_RXMAC_DEBUG3_TMP_PAUSE_CTR             (0xffffL<<16)
2970 
2971 #define BNX2_EMAC_RXMAC_DEBUG4              0x0000156c
2972 #define BNX2_EMAC_RXMAC_DEBUG4_TYPE_FIELD                (0xffffL<<0)
2973 #define BNX2_EMAC_RXMAC_DEBUG4_FILT_STATE                (0x3fL<<16)
2974 #define BNX2_EMAC_RXMAC_DEBUG4_FILT_STATE_IDLE           (0x0L<<16)
2975 #define BNX2_EMAC_RXMAC_DEBUG4_FILT_STATE_UMAC2          (0x1L<<16)
2976 #define BNX2_EMAC_RXMAC_DEBUG4_FILT_STATE_UMAC3          (0x2L<<16)
2977 #define BNX2_EMAC_RXMAC_DEBUG4_FILT_STATE_UNI            (0x3L<<16)
2978 #define BNX2_EMAC_RXMAC_DEBUG4_FILT_STATE_MMAC3          (0x5L<<16)
2979 #define BNX2_EMAC_RXMAC_DEBUG4_FILT_STATE_PSA1           (0x6L<<16)
2980 #define BNX2_EMAC_RXMAC_DEBUG4_FILT_STATE_MMAC2          (0x7L<<16)
2981 #define BNX2_EMAC_RXMAC_DEBUG4_FILT_STATE_PSA2           (0x7L<<16)
2982 #define BNX2_EMAC_RXMAC_DEBUG4_FILT_STATE_PSA3           (0x8L<<16)
2983 #define BNX2_EMAC_RXMAC_DEBUG4_FILT_STATE_MC2            (0x9L<<16)
2984 #define BNX2_EMAC_RXMAC_DEBUG4_FILT_STATE_MC3            (0xaL<<16)
2985 #define BNX2_EMAC_RXMAC_DEBUG4_FILT_STATE_MWAIT1         (0xeL<<16)
2986 #define BNX2_EMAC_RXMAC_DEBUG4_FILT_STATE_MWAIT2         (0xfL<<16)
2987 #define BNX2_EMAC_RXMAC_DEBUG4_FILT_STATE_MCHECK         (0x10L<<16)
2988 #define BNX2_EMAC_RXMAC_DEBUG4_FILT_STATE_MC             (0x11L<<16)
2989 #define BNX2_EMAC_RXMAC_DEBUG4_FILT_STATE_BC2            (0x12L<<16)
2990 #define BNX2_EMAC_RXMAC_DEBUG4_FILT_STATE_BC3            (0x13L<<16)
2991 #define BNX2_EMAC_RXMAC_DEBUG4_FILT_STATE_BSA1           (0x14L<<16)
2992 #define BNX2_EMAC_RXMAC_DEBUG4_FILT_STATE_BSA2           (0x15L<<16)
2993 #define BNX2_EMAC_RXMAC_DEBUG4_FILT_STATE_BSA3           (0x16L<<16)
2994 #define BNX2_EMAC_RXMAC_DEBUG4_FILT_STATE_BTYPE          (0x17L<<16)
2995 #define BNX2_EMAC_RXMAC_DEBUG4_FILT_STATE_BC             (0x18L<<16)
2996 #define BNX2_EMAC_RXMAC_DEBUG4_FILT_STATE_PTYPE          (0x19L<<16)
2997 #define BNX2_EMAC_RXMAC_DEBUG4_FILT_STATE_CMD            (0x1aL<<16)
2998 #define BNX2_EMAC_RXMAC_DEBUG4_FILT_STATE_MAC            (0x1bL<<16)
2999 #define BNX2_EMAC_RXMAC_DEBUG4_FILT_STATE_LATCH          (0x1cL<<16)
3000 #define BNX2_EMAC_RXMAC_DEBUG4_FILT_STATE_XOFF           (0x1dL<<16)
3001 #define BNX2_EMAC_RXMAC_DEBUG4_FILT_STATE_XON            (0x1eL<<16)
3002 #define BNX2_EMAC_RXMAC_DEBUG4_FILT_STATE_PAUSED         (0x1fL<<16)
3003 #define BNX2_EMAC_RXMAC_DEBUG4_FILT_STATE_NPAUSED        (0x20L<<16)
3004 #define BNX2_EMAC_RXMAC_DEBUG4_FILT_STATE_TTYPE          (0x21L<<16)
3005 #define BNX2_EMAC_RXMAC_DEBUG4_FILT_STATE_TVAL           (0x22L<<16)
3006 #define BNX2_EMAC_RXMAC_DEBUG4_FILT_STATE_USA1           (0x23L<<16)
3007 #define BNX2_EMAC_RXMAC_DEBUG4_FILT_STATE_USA2           (0x24L<<16)
3008 #define BNX2_EMAC_RXMAC_DEBUG4_FILT_STATE_USA3           (0x25L<<16)
3009 #define BNX2_EMAC_RXMAC_DEBUG4_FILT_STATE_UTYPE          (0x26L<<16)
3010 #define BNX2_EMAC_RXMAC_DEBUG4_FILT_STATE_UTTYPE         (0x27L<<16)
3011 #define BNX2_EMAC_RXMAC_DEBUG4_FILT_STATE_UTVAL          (0x28L<<16)
3012 #define BNX2_EMAC_RXMAC_DEBUG4_FILT_STATE_MTYPE          (0x29L<<16)
3013 #define BNX2_EMAC_RXMAC_DEBUG4_FILT_STATE_DROP           (0x2aL<<16)
3014 #define BNX2_EMAC_RXMAC_DEBUG4_DROP_PKT                  (1L<<22)
3015 #define BNX2_EMAC_RXMAC_DEBUG4_SLOT_FILLED               (1L<<23)
3016 #define BNX2_EMAC_RXMAC_DEBUG4_FALSE_CARRIER             (1L<<24)
3017 #define BNX2_EMAC_RXMAC_DEBUG4_LAST_DATA                 (1L<<25)
3018 #define BNX2_EMAC_RXMAC_DEBUG4_SFD_FOUND                 (1L<<26)
3019 #define BNX2_EMAC_RXMAC_DEBUG4_ADVANCE                   (1L<<27)
3020 #define BNX2_EMAC_RXMAC_DEBUG4_START                     (1L<<28)
3021 
3022 #define BNX2_EMAC_RXMAC_DEBUG5              0x00001570
3023 #define BNX2_EMAC_RXMAC_DEBUG5_PS_IDISM                  (0x7L<<0)
3024 #define BNX2_EMAC_RXMAC_DEBUG5_PS_IDISM_IDLE             (0L<<0)
3025 #define BNX2_EMAC_RXMAC_DEBUG5_PS_IDISM_WAIT_EOF         (1L<<0)
3026 #define BNX2_EMAC_RXMAC_DEBUG5_PS_IDISM_WAIT_STAT        (2L<<0)
3027 #define BNX2_EMAC_RXMAC_DEBUG5_PS_IDISM_SET_EOF4FCRC     (3L<<0)
3028 #define BNX2_EMAC_RXMAC_DEBUG5_PS_IDISM_SET_EOF4RDE      (4L<<0)
3029 #define BNX2_EMAC_RXMAC_DEBUG5_PS_IDISM_SET_EOF4ALL      (5L<<0)
3030 #define BNX2_EMAC_RXMAC_DEBUG5_PS_IDISM_1WD_WAIT_STAT    (6L<<0)
3031 #define BNX2_EMAC_RXMAC_DEBUG5_CCODE_BUF1                (0x7L<<4)
3032 #define BNX2_EMAC_RXMAC_DEBUG5_CCODE_BUF1_VDW            (0x0L<<4)
3033 #define BNX2_EMAC_RXMAC_DEBUG5_CCODE_BUF1_STAT           (0x1L<<4)
3034 #define BNX2_EMAC_RXMAC_DEBUG5_CCODE_BUF1_AEOF           (0x2L<<4)
3035 #define BNX2_EMAC_RXMAC_DEBUG5_CCODE_BUF1_NEOF           (0x3L<<4)
3036 #define BNX2_EMAC_RXMAC_DEBUG5_CCODE_BUF1_SOF            (0x4L<<4)
3037 #define BNX2_EMAC_RXMAC_DEBUG5_CCODE_BUF1_SAEOF          (0x6L<<4)
3038 #define BNX2_EMAC_RXMAC_DEBUG5_CCODE_BUF1_SNEOF          (0x7L<<4)
3039 #define BNX2_EMAC_RXMAC_DEBUG5_EOF_DETECTED              (1L<<7)
3040 #define BNX2_EMAC_RXMAC_DEBUG5_CCODE_BUF0                (0x7L<<8)
3041 #define BNX2_EMAC_RXMAC_DEBUG5_RPM_IDI_FIFO_FULL         (1L<<11)
3042 #define BNX2_EMAC_RXMAC_DEBUG5_LOAD_CCODE                (1L<<12)
3043 #define BNX2_EMAC_RXMAC_DEBUG5_LOAD_DATA                 (1L<<13)
3044 #define BNX2_EMAC_RXMAC_DEBUG5_LOAD_STAT                 (1L<<14)
3045 #define BNX2_EMAC_RXMAC_DEBUG5_CLR_STAT                  (1L<<15)
3046 #define BNX2_EMAC_RXMAC_DEBUG5_IDI_RPM_CCODE             (0x3L<<16)
3047 #define BNX2_EMAC_RXMAC_DEBUG5_IDI_RPM_ACCEPT            (1L<<19)
3048 #define BNX2_EMAC_RXMAC_DEBUG5_FMLEN                     (0xfffL<<20)
3049 
3050 #define BNX2_EMAC_RX_STAT_FALSECARRIERERRORS        0x00001574
3051 #define BNX2_EMAC_RX_STAT_AC0               0x00001580
3052 #define BNX2_EMAC_RX_STAT_AC1               0x00001584
3053 #define BNX2_EMAC_RX_STAT_AC2               0x00001588
3054 #define BNX2_EMAC_RX_STAT_AC3               0x0000158c
3055 #define BNX2_EMAC_RX_STAT_AC4               0x00001590
3056 #define BNX2_EMAC_RX_STAT_AC5               0x00001594
3057 #define BNX2_EMAC_RX_STAT_AC6               0x00001598
3058 #define BNX2_EMAC_RX_STAT_AC7               0x0000159c
3059 #define BNX2_EMAC_RX_STAT_AC8               0x000015a0
3060 #define BNX2_EMAC_RX_STAT_AC9               0x000015a4
3061 #define BNX2_EMAC_RX_STAT_AC10              0x000015a8
3062 #define BNX2_EMAC_RX_STAT_AC11              0x000015ac
3063 #define BNX2_EMAC_RX_STAT_AC12              0x000015b0
3064 #define BNX2_EMAC_RX_STAT_AC13              0x000015b4
3065 #define BNX2_EMAC_RX_STAT_AC14              0x000015b8
3066 #define BNX2_EMAC_RX_STAT_AC15              0x000015bc
3067 #define BNX2_EMAC_RX_STAT_AC16              0x000015c0
3068 #define BNX2_EMAC_RX_STAT_AC17              0x000015c4
3069 #define BNX2_EMAC_RX_STAT_AC18              0x000015c8
3070 #define BNX2_EMAC_RX_STAT_AC19              0x000015cc
3071 #define BNX2_EMAC_RX_STAT_AC20              0x000015d0
3072 #define BNX2_EMAC_RX_STAT_AC21              0x000015d4
3073 #define BNX2_EMAC_RX_STAT_AC22              0x000015d8
3074 #define BNX2_EMAC_RXMAC_SUC_DBG_OVERRUNVEC      0x000015dc
3075 #define BNX2_EMAC_RX_STAT_AC_28             0x000015f4
3076 #define BNX2_EMAC_TX_STAT_IFHCOUTOCTETS         0x00001600
3077 #define BNX2_EMAC_TX_STAT_IFHCOUTBADOCTETS      0x00001604
3078 #define BNX2_EMAC_TX_STAT_ETHERSTATSCOLLISIONS      0x00001608
3079 #define BNX2_EMAC_TX_STAT_OUTXONSENT            0x0000160c
3080 #define BNX2_EMAC_TX_STAT_OUTXOFFSENT           0x00001610
3081 #define BNX2_EMAC_TX_STAT_FLOWCONTROLDONE       0x00001614
3082 #define BNX2_EMAC_TX_STAT_DOT3STATSSINGLECOLLISIONFRAMES    0x00001618
3083 #define BNX2_EMAC_TX_STAT_DOT3STATSMULTIPLECOLLISIONFRAMES  0x0000161c
3084 #define BNX2_EMAC_TX_STAT_DOT3STATSDEFERREDTRANSMISSIONS    0x00001620
3085 #define BNX2_EMAC_TX_STAT_DOT3STATSEXCESSIVECOLLISIONS  0x00001624
3086 #define BNX2_EMAC_TX_STAT_DOT3STATSLATECOLLISIONS   0x00001628
3087 #define BNX2_EMAC_TX_STAT_IFHCOUTUCASTPKTS      0x0000162c
3088 #define BNX2_EMAC_TX_STAT_IFHCOUTMULTICASTPKTS      0x00001630
3089 #define BNX2_EMAC_TX_STAT_IFHCOUTBROADCASTPKTS      0x00001634
3090 #define BNX2_EMAC_TX_STAT_ETHERSTATSPKTS64OCTETS    0x00001638
3091 #define BNX2_EMAC_TX_STAT_ETHERSTATSPKTS65OCTETSTO127OCTETS 0x0000163c
3092 #define BNX2_EMAC_TX_STAT_ETHERSTATSPKTS128OCTETSTO255OCTETS    0x00001640
3093 #define BNX2_EMAC_TX_STAT_ETHERSTATSPKTS256OCTETSTO511OCTETS    0x00001644
3094 #define BNX2_EMAC_TX_STAT_ETHERSTATSPKTS512OCTETSTO1023OCTETS   0x00001648
3095 #define BNX2_EMAC_TX_STAT_ETHERSTATSPKTS1024OCTETSTO1522OCTETS  0x0000164c
3096 #define BNX2_EMAC_TX_STAT_ETHERSTATSPKTSOVER1522OCTETS  0x00001650
3097 #define BNX2_EMAC_TX_STAT_DOT3STATSINTERNALMACTRANSMITERRORS    0x00001654
3098 #define BNX2_EMAC_TXMAC_DEBUG0              0x00001658
3099 #define BNX2_EMAC_TXMAC_DEBUG1              0x0000165c
3100 #define BNX2_EMAC_TXMAC_DEBUG1_ODI_STATE                 (0xfL<<0)
3101 #define BNX2_EMAC_TXMAC_DEBUG1_ODI_STATE_IDLE            (0x0L<<0)
3102 #define BNX2_EMAC_TXMAC_DEBUG1_ODI_STATE_START0          (0x1L<<0)
3103 #define BNX2_EMAC_TXMAC_DEBUG1_ODI_STATE_DATA0           (0x4L<<0)
3104 #define BNX2_EMAC_TXMAC_DEBUG1_ODI_STATE_DATA1           (0x5L<<0)
3105 #define BNX2_EMAC_TXMAC_DEBUG1_ODI_STATE_DATA2           (0x6L<<0)
3106 #define BNX2_EMAC_TXMAC_DEBUG1_ODI_STATE_DATA3           (0x7L<<0)
3107 #define BNX2_EMAC_TXMAC_DEBUG1_ODI_STATE_WAIT0           (0x8L<<0)
3108 #define BNX2_EMAC_TXMAC_DEBUG1_ODI_STATE_WAIT1           (0x9L<<0)
3109 #define BNX2_EMAC_TXMAC_DEBUG1_CRS_ENABLE                (1L<<4)
3110 #define BNX2_EMAC_TXMAC_DEBUG1_BAD_CRC                   (1L<<5)
3111 #define BNX2_EMAC_TXMAC_DEBUG1_SE_COUNTER                (0xfL<<6)
3112 #define BNX2_EMAC_TXMAC_DEBUG1_SEND_PAUSE                (1L<<10)
3113 #define BNX2_EMAC_TXMAC_DEBUG1_LATE_COLLISION            (1L<<11)
3114 #define BNX2_EMAC_TXMAC_DEBUG1_MAX_DEFER                 (1L<<12)
3115 #define BNX2_EMAC_TXMAC_DEBUG1_DEFERRED                  (1L<<13)
3116 #define BNX2_EMAC_TXMAC_DEBUG1_ONE_BYTE                  (1L<<14)
3117 #define BNX2_EMAC_TXMAC_DEBUG1_IPG_TIME                  (0xfL<<15)
3118 #define BNX2_EMAC_TXMAC_DEBUG1_SLOT_TIME                 (0xffL<<19)
3119 
3120 #define BNX2_EMAC_TXMAC_DEBUG2              0x00001660
3121 #define BNX2_EMAC_TXMAC_DEBUG2_BACK_OFF                  (0x3ffL<<0)
3122 #define BNX2_EMAC_TXMAC_DEBUG2_BYTE_COUNT                (0xffffL<<10)
3123 #define BNX2_EMAC_TXMAC_DEBUG2_COL_COUNT                 (0x1fL<<26)
3124 #define BNX2_EMAC_TXMAC_DEBUG2_COL_BIT                   (1L<<31)
3125 
3126 #define BNX2_EMAC_TXMAC_DEBUG3              0x00001664
3127 #define BNX2_EMAC_TXMAC_DEBUG3_SM_STATE                  (0xfL<<0)
3128 #define BNX2_EMAC_TXMAC_DEBUG3_SM_STATE_IDLE             (0x0L<<0)
3129 #define BNX2_EMAC_TXMAC_DEBUG3_SM_STATE_PRE1             (0x1L<<0)
3130 #define BNX2_EMAC_TXMAC_DEBUG3_SM_STATE_PRE2             (0x2L<<0)
3131 #define BNX2_EMAC_TXMAC_DEBUG3_SM_STATE_SFD              (0x3L<<0)
3132 #define BNX2_EMAC_TXMAC_DEBUG3_SM_STATE_DATA             (0x4L<<0)
3133 #define BNX2_EMAC_TXMAC_DEBUG3_SM_STATE_CRC1             (0x5L<<0)
3134 #define BNX2_EMAC_TXMAC_DEBUG3_SM_STATE_CRC2             (0x6L<<0)
3135 #define BNX2_EMAC_TXMAC_DEBUG3_SM_STATE_EXT              (0x7L<<0)
3136 #define BNX2_EMAC_TXMAC_DEBUG3_SM_STATE_STATB            (0x8L<<0)
3137 #define BNX2_EMAC_TXMAC_DEBUG3_SM_STATE_STATG            (0x9L<<0)
3138 #define BNX2_EMAC_TXMAC_DEBUG3_SM_STATE_JAM              (0xaL<<0)
3139 #define BNX2_EMAC_TXMAC_DEBUG3_SM_STATE_EJAM             (0xbL<<0)
3140 #define BNX2_EMAC_TXMAC_DEBUG3_SM_STATE_BJAM             (0xcL<<0)
3141 #define BNX2_EMAC_TXMAC_DEBUG3_SM_STATE_SWAIT            (0xdL<<0)
3142 #define BNX2_EMAC_TXMAC_DEBUG3_SM_STATE_BACKOFF          (0xeL<<0)
3143 #define BNX2_EMAC_TXMAC_DEBUG3_FILT_STATE                (0x7L<<4)
3144 #define BNX2_EMAC_TXMAC_DEBUG3_FILT_STATE_IDLE           (0x0L<<4)
3145 #define BNX2_EMAC_TXMAC_DEBUG3_FILT_STATE_WAIT           (0x1L<<4)
3146 #define BNX2_EMAC_TXMAC_DEBUG3_FILT_STATE_UNI            (0x2L<<4)
3147 #define BNX2_EMAC_TXMAC_DEBUG3_FILT_STATE_MC             (0x3L<<4)
3148 #define BNX2_EMAC_TXMAC_DEBUG3_FILT_STATE_BC2            (0x4L<<4)
3149 #define BNX2_EMAC_TXMAC_DEBUG3_FILT_STATE_BC3            (0x5L<<4)
3150 #define BNX2_EMAC_TXMAC_DEBUG3_FILT_STATE_BC             (0x6L<<4)
3151 #define BNX2_EMAC_TXMAC_DEBUG3_CRS_DONE                  (1L<<7)
3152 #define BNX2_EMAC_TXMAC_DEBUG3_XOFF                      (1L<<8)
3153 #define BNX2_EMAC_TXMAC_DEBUG3_SE_COUNTER                (0xfL<<9)
3154 #define BNX2_EMAC_TXMAC_DEBUG3_QUANTA_COUNTER            (0x1fL<<13)
3155 
3156 #define BNX2_EMAC_TXMAC_DEBUG4              0x00001668
3157 #define BNX2_EMAC_TXMAC_DEBUG4_PAUSE_COUNTER             (0xffffL<<0)
3158 #define BNX2_EMAC_TXMAC_DEBUG4_PAUSE_STATE               (0xfL<<16)
3159 #define BNX2_EMAC_TXMAC_DEBUG4_PAUSE_STATE_IDLE          (0x0L<<16)
3160 #define BNX2_EMAC_TXMAC_DEBUG4_PAUSE_STATE_MCA1          (0x2L<<16)
3161 #define BNX2_EMAC_TXMAC_DEBUG4_PAUSE_STATE_MCA2          (0x3L<<16)
3162 #define BNX2_EMAC_TXMAC_DEBUG4_PAUSE_STATE_SRC3          (0x4L<<16)
3163 #define BNX2_EMAC_TXMAC_DEBUG4_PAUSE_STATE_SRC2          (0x5L<<16)
3164 #define BNX2_EMAC_TXMAC_DEBUG4_PAUSE_STATE_MCA3          (0x6L<<16)
3165 #define BNX2_EMAC_TXMAC_DEBUG4_PAUSE_STATE_SRC1          (0x7L<<16)
3166 #define BNX2_EMAC_TXMAC_DEBUG4_PAUSE_STATE_CRC1          (0x8L<<16)
3167 #define BNX2_EMAC_TXMAC_DEBUG4_PAUSE_STATE_CRC2          (0x9L<<16)
3168 #define BNX2_EMAC_TXMAC_DEBUG4_PAUSE_STATE_TIME          (0xaL<<16)
3169 #define BNX2_EMAC_TXMAC_DEBUG4_PAUSE_STATE_TYPE          (0xcL<<16)
3170 #define BNX2_EMAC_TXMAC_DEBUG4_PAUSE_STATE_WAIT          (0xdL<<16)
3171 #define BNX2_EMAC_TXMAC_DEBUG4_PAUSE_STATE_CMD           (0xeL<<16)
3172 #define BNX2_EMAC_TXMAC_DEBUG4_STATS0_VALID              (1L<<20)
3173 #define BNX2_EMAC_TXMAC_DEBUG4_APPEND_CRC                (1L<<21)
3174 #define BNX2_EMAC_TXMAC_DEBUG4_SLOT_FILLED               (1L<<22)
3175 #define BNX2_EMAC_TXMAC_DEBUG4_MAX_DEFER                 (1L<<23)
3176 #define BNX2_EMAC_TXMAC_DEBUG4_SEND_EXTEND               (1L<<24)
3177 #define BNX2_EMAC_TXMAC_DEBUG4_SEND_PADDING              (1L<<25)
3178 #define BNX2_EMAC_TXMAC_DEBUG4_EOF_LOC                   (1L<<26)
3179 #define BNX2_EMAC_TXMAC_DEBUG4_COLLIDING                 (1L<<27)
3180 #define BNX2_EMAC_TXMAC_DEBUG4_COL_IN                    (1L<<28)
3181 #define BNX2_EMAC_TXMAC_DEBUG4_BURSTING                  (1L<<29)
3182 #define BNX2_EMAC_TXMAC_DEBUG4_ADVANCE                   (1L<<30)
3183 #define BNX2_EMAC_TXMAC_DEBUG4_GO                        (1L<<31)
3184 
3185 #define BNX2_EMAC_TX_STAT_AC0               0x00001680
3186 #define BNX2_EMAC_TX_STAT_AC1               0x00001684
3187 #define BNX2_EMAC_TX_STAT_AC2               0x00001688
3188 #define BNX2_EMAC_TX_STAT_AC3               0x0000168c
3189 #define BNX2_EMAC_TX_STAT_AC4               0x00001690
3190 #define BNX2_EMAC_TX_STAT_AC5               0x00001694
3191 #define BNX2_EMAC_TX_STAT_AC6               0x00001698
3192 #define BNX2_EMAC_TX_STAT_AC7               0x0000169c
3193 #define BNX2_EMAC_TX_STAT_AC8               0x000016a0
3194 #define BNX2_EMAC_TX_STAT_AC9               0x000016a4
3195 #define BNX2_EMAC_TX_STAT_AC10              0x000016a8
3196 #define BNX2_EMAC_TX_STAT_AC11              0x000016ac
3197 #define BNX2_EMAC_TX_STAT_AC12              0x000016b0
3198 #define BNX2_EMAC_TX_STAT_AC13              0x000016b4
3199 #define BNX2_EMAC_TX_STAT_AC14              0x000016b8
3200 #define BNX2_EMAC_TX_STAT_AC15              0x000016bc
3201 #define BNX2_EMAC_TX_STAT_AC16              0x000016c0
3202 #define BNX2_EMAC_TX_STAT_AC17              0x000016c4
3203 #define BNX2_EMAC_TX_STAT_AC18              0x000016c8
3204 #define BNX2_EMAC_TX_STAT_AC19              0x000016cc
3205 #define BNX2_EMAC_TX_STAT_AC20              0x000016d0
3206 #define BNX2_EMAC_TXMAC_SUC_DBG_OVERRUNVEC      0x000016d8
3207 #define BNX2_EMAC_TX_RATE_LIMIT_CTRL            0x000016fc
3208 #define BNX2_EMAC_TX_RATE_LIMIT_CTRL_TX_THROTTLE_INC     (0x7fL<<0)
3209 #define BNX2_EMAC_TX_RATE_LIMIT_CTRL_TX_THROTTLE_NUM     (0x7fL<<16)
3210 #define BNX2_EMAC_TX_RATE_LIMIT_CTRL_RATE_LIMITER_EN     (1L<<31)
3211 
3212 
3213 /*
3214  *  rpm_reg definition
3215  *  offset: 0x1800
3216  */
3217 #define BNX2_RPM_COMMAND                0x00001800
3218 #define BNX2_RPM_COMMAND_ENABLED                         (1L<<0)
3219 #define BNX2_RPM_COMMAND_OVERRUN_ABORT                   (1L<<4)
3220 
3221 #define BNX2_RPM_STATUS                 0x00001804
3222 #define BNX2_RPM_STATUS_MBUF_WAIT                        (1L<<0)
3223 #define BNX2_RPM_STATUS_FREE_WAIT                        (1L<<1)
3224 
3225 #define BNX2_RPM_CONFIG                 0x00001808
3226 #define BNX2_RPM_CONFIG_NO_PSD_HDR_CKSUM                 (1L<<0)
3227 #define BNX2_RPM_CONFIG_ACPI_ENA                         (1L<<1)
3228 #define BNX2_RPM_CONFIG_ACPI_KEEP                        (1L<<2)
3229 #define BNX2_RPM_CONFIG_MP_KEEP                          (1L<<3)
3230 #define BNX2_RPM_CONFIG_SORT_VECT_VAL                    (0xfL<<4)
3231 #define BNX2_RPM_CONFIG_DISABLE_WOL_ASSERT               (1L<<30)
3232 #define BNX2_RPM_CONFIG_IGNORE_VLAN                      (1L<<31)
3233 
3234 #define BNX2_RPM_MGMT_PKT_CTRL              0x0000180c
3235 #define BNX2_RPM_MGMT_PKT_CTRL_MGMT_SORT                 (0xfL<<0)
3236 #define BNX2_RPM_MGMT_PKT_CTRL_MGMT_RULE                 (0xfL<<4)
3237 #define BNX2_RPM_MGMT_PKT_CTRL_MGMT_DISCARD_EN           (1L<<30)
3238 #define BNX2_RPM_MGMT_PKT_CTRL_MGMT_EN                   (1L<<31)
3239 
3240 #define BNX2_RPM_VLAN_MATCH0                0x00001810
3241 #define BNX2_RPM_VLAN_MATCH0_RPM_VLAN_MTCH0_VALUE        (0xfffL<<0)
3242 
3243 #define BNX2_RPM_VLAN_MATCH1                0x00001814
3244 #define BNX2_RPM_VLAN_MATCH1_RPM_VLAN_MTCH1_VALUE        (0xfffL<<0)
3245 
3246 #define BNX2_RPM_VLAN_MATCH2                0x00001818
3247 #define BNX2_RPM_VLAN_MATCH2_RPM_VLAN_MTCH2_VALUE        (0xfffL<<0)
3248 
3249 #define BNX2_RPM_VLAN_MATCH3                0x0000181c
3250 #define BNX2_RPM_VLAN_MATCH3_RPM_VLAN_MTCH3_VALUE        (0xfffL<<0)
3251 
3252 #define BNX2_RPM_SORT_USER0             0x00001820
3253 #define BNX2_RPM_SORT_USER0_PM_EN                        (0xffffL<<0)
3254 #define BNX2_RPM_SORT_USER0_BC_EN                        (1L<<16)
3255 #define BNX2_RPM_SORT_USER0_MC_EN                        (1L<<17)
3256 #define BNX2_RPM_SORT_USER0_MC_HSH_EN                    (1L<<18)
3257 #define BNX2_RPM_SORT_USER0_PROM_EN                      (1L<<19)
3258 #define BNX2_RPM_SORT_USER0_VLAN_EN                      (0xfL<<20)
3259 #define BNX2_RPM_SORT_USER0_PROM_VLAN                    (1L<<24)
3260 #define BNX2_RPM_SORT_USER0_VLAN_NOTMATCH                (1L<<25)
3261 #define BNX2_RPM_SORT_USER0_ENA                          (1L<<31)
3262 
3263 #define BNX2_RPM_SORT_USER1             0x00001824
3264 #define BNX2_RPM_SORT_USER1_PM_EN                        (0xffffL<<0)
3265 #define BNX2_RPM_SORT_USER1_BC_EN                        (1L<<16)
3266 #define BNX2_RPM_SORT_USER1_MC_EN                        (1L<<17)
3267 #define BNX2_RPM_SORT_USER1_MC_HSH_EN                    (1L<<18)
3268 #define BNX2_RPM_SORT_USER1_PROM_EN                      (1L<<19)
3269 #define BNX2_RPM_SORT_USER1_VLAN_EN                      (0xfL<<20)
3270 #define BNX2_RPM_SORT_USER1_PROM_VLAN                    (1L<<24)
3271 #define BNX2_RPM_SORT_USER1_ENA                          (1L<<31)
3272 
3273 #define BNX2_RPM_SORT_USER2             0x00001828
3274 #define BNX2_RPM_SORT_USER2_PM_EN                        (0xffffL<<0)
3275 #define BNX2_RPM_SORT_USER2_BC_EN                        (1L<<16)
3276 #define BNX2_RPM_SORT_USER2_MC_EN                        (1L<<17)
3277 #define BNX2_RPM_SORT_USER2_MC_HSH_EN                    (1L<<18)
3278 #define BNX2_RPM_SORT_USER2_PROM_EN                      (1L<<19)
3279 #define BNX2_RPM_SORT_USER2_VLAN_EN                      (0xfL<<20)
3280 #define BNX2_RPM_SORT_USER2_PROM_VLAN                    (1L<<24)
3281 #define BNX2_RPM_SORT_USER2_ENA                          (1L<<31)
3282 
3283 #define BNX2_RPM_SORT_USER3             0x0000182c
3284 #define BNX2_RPM_SORT_USER3_PM_EN                        (0xffffL<<0)
3285 #define BNX2_RPM_SORT_USER3_BC_EN                        (1L<<16)
3286 #define BNX2_RPM_SORT_USER3_MC_EN            (1L<<17)
3287 #define BNX2_RPM_SORT_USER3_MC_HSH_EN            (1L<<18)
3288 #define BNX2_RPM_SORT_USER3_PROM_EN          (1L<<19)
3289 #define BNX2_RPM_SORT_USER3_VLAN_EN          (0xfL<<20)
3290 #define BNX2_RPM_SORT_USER3_PROM_VLAN            (1L<<24)
3291 #define BNX2_RPM_SORT_USER3_ENA              (1L<<31)
3292 
3293 #define BNX2_RPM_STAT_L2_FILTER_DISCARDS        0x00001840
3294 #define BNX2_RPM_STAT_RULE_CHECKER_DISCARDS     0x00001844
3295 #define BNX2_RPM_STAT_IFINFTQDISCARDS           0x00001848
3296 #define BNX2_RPM_STAT_IFINMBUFDISCARD           0x0000184c
3297 #define BNX2_RPM_STAT_RULE_CHECKER_P4_HIT       0x00001850
3298 #define BNX2_RPM_IPV6_PROGRAMMABLE_EXTENSION0       0x00001854
3299 #define BNX2_RPM_IPV6_PROGRAMMABLE_EXTENSION0_NEXT_HEADER_LEN    (0xffL<<0)
3300 #define BNX2_RPM_IPV6_PROGRAMMABLE_EXTENSION0_NEXT_HEADER    (0xffL<<16)
3301 #define BNX2_RPM_IPV6_PROGRAMMABLE_EXTENSION0_NEXT_HEADER_LEN_TYPE   (1L<<30)
3302 #define BNX2_RPM_IPV6_PROGRAMMABLE_EXTENSION0_NEXT_HEADER_EN     (1L<<31)
3303 
3304 #define BNX2_RPM_IPV6_PROGRAMMABLE_EXTENSION1       0x00001858
3305 #define BNX2_RPM_IPV6_PROGRAMMABLE_EXTENSION1_NEXT_HEADER_LEN    (0xffL<<0)
3306 #define BNX2_RPM_IPV6_PROGRAMMABLE_EXTENSION1_NEXT_HEADER    (0xffL<<16)
3307 #define BNX2_RPM_IPV6_PROGRAMMABLE_EXTENSION1_NEXT_HEADER_LEN_TYPE   (1L<<30)
3308 #define BNX2_RPM_IPV6_PROGRAMMABLE_EXTENSION1_NEXT_HEADER_EN     (1L<<31)
3309 
3310 #define BNX2_RPM_IPV6_PROGRAMMABLE_EXTENSION2       0x0000185c
3311 #define BNX2_RPM_IPV6_PROGRAMMABLE_EXTENSION2_NEXT_HEADER_LEN    (0xffL<<0)
3312 #define BNX2_RPM_IPV6_PROGRAMMABLE_EXTENSION2_NEXT_HEADER    (0xffL<<16)
3313 #define BNX2_RPM_IPV6_PROGRAMMABLE_EXTENSION2_NEXT_HEADER_LEN_TYPE   (1L<<30)
3314 #define BNX2_RPM_IPV6_PROGRAMMABLE_EXTENSION2_NEXT_HEADER_EN     (1L<<31)
3315 
3316 #define BNX2_RPM_IPV6_PROGRAMMABLE_EXTENSION3       0x00001860
3317 #define BNX2_RPM_IPV6_PROGRAMMABLE_EXTENSION3_NEXT_HEADER_LEN    (0xffL<<0)
3318 #define BNX2_RPM_IPV6_PROGRAMMABLE_EXTENSION3_NEXT_HEADER    (0xffL<<16)
3319 #define BNX2_RPM_IPV6_PROGRAMMABLE_EXTENSION3_NEXT_HEADER_LEN_TYPE   (1L<<30)
3320 #define BNX2_RPM_IPV6_PROGRAMMABLE_EXTENSION3_NEXT_HEADER_EN     (1L<<31)
3321 
3322 #define BNX2_RPM_IPV6_PROGRAMMABLE_EXTENSION4       0x00001864
3323 #define BNX2_RPM_IPV6_PROGRAMMABLE_EXTENSION4_NEXT_HEADER_LEN    (0xffL<<0)
3324 #define BNX2_RPM_IPV6_PROGRAMMABLE_EXTENSION4_NEXT_HEADER    (0xffL<<16)
3325 #define BNX2_RPM_IPV6_PROGRAMMABLE_EXTENSION4_NEXT_HEADER_LEN_TYPE   (1L<<30)
3326 #define BNX2_RPM_IPV6_PROGRAMMABLE_EXTENSION4_NEXT_HEADER_EN     (1L<<31)
3327 
3328 #define BNX2_RPM_IPV6_PROGRAMMABLE_EXTENSION5       0x00001868
3329 #define BNX2_RPM_IPV6_PROGRAMMABLE_EXTENSION5_NEXT_HEADER_LEN    (0xffL<<0)
3330 #define BNX2_RPM_IPV6_PROGRAMMABLE_EXTENSION5_NEXT_HEADER    (0xffL<<16)
3331 #define BNX2_RPM_IPV6_PROGRAMMABLE_EXTENSION5_NEXT_HEADER_LEN_TYPE   (1L<<30)
3332 #define BNX2_RPM_IPV6_PROGRAMMABLE_EXTENSION5_NEXT_HEADER_EN     (1L<<31)
3333 
3334 #define BNX2_RPM_IPV6_PROGRAMMABLE_EXTENSION6       0x0000186c
3335 #define BNX2_RPM_IPV6_PROGRAMMABLE_EXTENSION6_NEXT_HEADER_LEN    (0xffL<<0)
3336 #define BNX2_RPM_IPV6_PROGRAMMABLE_EXTENSION6_NEXT_HEADER    (0xffL<<16)
3337 #define BNX2_RPM_IPV6_PROGRAMMABLE_EXTENSION6_NEXT_HEADER_LEN_TYPE   (1L<<30)
3338 #define BNX2_RPM_IPV6_PROGRAMMABLE_EXTENSION6_NEXT_HEADER_EN     (1L<<31)
3339 
3340 #define BNX2_RPM_IPV6_PROGRAMMABLE_EXTENSION7       0x00001870
3341 #define BNX2_RPM_IPV6_PROGRAMMABLE_EXTENSION7_NEXT_HEADER_LEN    (0xffL<<0)
3342 #define BNX2_RPM_IPV6_PROGRAMMABLE_EXTENSION7_NEXT_HEADER    (0xffL<<16)
3343 #define BNX2_RPM_IPV6_PROGRAMMABLE_EXTENSION7_NEXT_HEADER_LEN_TYPE   (1L<<30)
3344 #define BNX2_RPM_IPV6_PROGRAMMABLE_EXTENSION7_NEXT_HEADER_EN     (1L<<31)
3345 
3346 #define BNX2_RPM_STAT_AC0               0x00001880
3347 #define BNX2_RPM_STAT_AC1               0x00001884
3348 #define BNX2_RPM_STAT_AC2               0x00001888
3349 #define BNX2_RPM_STAT_AC3               0x0000188c
3350 #define BNX2_RPM_STAT_AC4               0x00001890
3351 #define BNX2_RPM_RC_CNTL_16             0x000018e0
3352 #define BNX2_RPM_RC_CNTL_16_OFFSET           (0xffL<<0)
3353 #define BNX2_RPM_RC_CNTL_16_CLASS            (0x7L<<8)
3354 #define BNX2_RPM_RC_CNTL_16_PRIORITY             (1L<<11)
3355 #define BNX2_RPM_RC_CNTL_16_P4               (1L<<12)
3356 #define BNX2_RPM_RC_CNTL_16_HDR_TYPE             (0x7L<<13)
3357 #define BNX2_RPM_RC_CNTL_16_HDR_TYPE_START       (0L<<13)
3358 #define BNX2_RPM_RC_CNTL_16_HDR_TYPE_IP          (1L<<13)
3359 #define BNX2_RPM_RC_CNTL_16_HDR_TYPE_TCP         (2L<<13)
3360 #define BNX2_RPM_RC_CNTL_16_HDR_TYPE_UDP         (3L<<13)
3361 #define BNX2_RPM_RC_CNTL_16_HDR_TYPE_DATA        (4L<<13)
3362 #define BNX2_RPM_RC_CNTL_16_HDR_TYPE_TCP_UDP         (5L<<13)
3363 #define BNX2_RPM_RC_CNTL_16_HDR_TYPE_ICMPV6      (6L<<13)
3364 #define BNX2_RPM_RC_CNTL_16_COMP             (0x3L<<16)
3365 #define BNX2_RPM_RC_CNTL_16_COMP_EQUAL           (0L<<16)
3366 #define BNX2_RPM_RC_CNTL_16_COMP_NEQUAL          (1L<<16)
3367 #define BNX2_RPM_RC_CNTL_16_COMP_GREATER         (2L<<16)
3368 #define BNX2_RPM_RC_CNTL_16_COMP_LESS            (3L<<16)
3369 #define BNX2_RPM_RC_CNTL_16_MAP              (1L<<18)
3370 #define BNX2_RPM_RC_CNTL_16_SBIT             (1L<<19)
3371 #define BNX2_RPM_RC_CNTL_16_CMDSEL           (0x1fL<<20)
3372 #define BNX2_RPM_RC_CNTL_16_DISCARD          (1L<<25)
3373 #define BNX2_RPM_RC_CNTL_16_MASK             (1L<<26)
3374 #define BNX2_RPM_RC_CNTL_16_P1               (1L<<27)
3375 #define BNX2_RPM_RC_CNTL_16_P2               (1L<<28)
3376 #define BNX2_RPM_RC_CNTL_16_P3               (1L<<29)
3377 #define BNX2_RPM_RC_CNTL_16_NBIT             (1L<<30)
3378 
3379 #define BNX2_RPM_RC_VALUE_MASK_16           0x000018e4
3380 #define BNX2_RPM_RC_VALUE_MASK_16_VALUE          (0xffffL<<0)
3381 #define BNX2_RPM_RC_VALUE_MASK_16_MASK           (0xffffL<<16)
3382 
3383 #define BNX2_RPM_RC_CNTL_17             0x000018e8
3384 #define BNX2_RPM_RC_CNTL_17_OFFSET           (0xffL<<0)
3385 #define BNX2_RPM_RC_CNTL_17_CLASS            (0x7L<<8)
3386 #define BNX2_RPM_RC_CNTL_17_PRIORITY             (1L<<11)
3387 #define BNX2_RPM_RC_CNTL_17_P4               (1L<<12)
3388 #define BNX2_RPM_RC_CNTL_17_HDR_TYPE             (0x7L<<13)
3389 #define BNX2_RPM_RC_CNTL_17_HDR_TYPE_START       (0L<<13)
3390 #define BNX2_RPM_RC_CNTL_17_HDR_TYPE_IP          (1L<<13)
3391 #define BNX2_RPM_RC_CNTL_17_HDR_TYPE_TCP         (2L<<13)
3392 #define BNX2_RPM_RC_CNTL_17_HDR_TYPE_UDP         (3L<<13)
3393 #define BNX2_RPM_RC_CNTL_17_HDR_TYPE_DATA        (4L<<13)
3394 #define BNX2_RPM_RC_CNTL_17_HDR_TYPE_TCP_UDP         (5L<<13)
3395 #define BNX2_RPM_RC_CNTL_17_HDR_TYPE_ICMPV6      (6L<<13)
3396 #define BNX2_RPM_RC_CNTL_17_COMP             (0x3L<<16)
3397 #define BNX2_RPM_RC_CNTL_17_COMP_EQUAL           (0L<<16)
3398 #define BNX2_RPM_RC_CNTL_17_COMP_NEQUAL          (1L<<16)
3399 #define BNX2_RPM_RC_CNTL_17_COMP_GREATER         (2L<<16)
3400 #define BNX2_RPM_RC_CNTL_17_COMP_LESS            (3L<<16)
3401 #define BNX2_RPM_RC_CNTL_17_MAP              (1L<<18)
3402 #define BNX2_RPM_RC_CNTL_17_SBIT             (1L<<19)
3403 #define BNX2_RPM_RC_CNTL_17_CMDSEL           (0x1fL<<20)
3404 #define BNX2_RPM_RC_CNTL_17_DISCARD          (1L<<25)
3405 #define BNX2_RPM_RC_CNTL_17_MASK             (1L<<26)
3406 #define BNX2_RPM_RC_CNTL_17_P1               (1L<<27)
3407 #define BNX2_RPM_RC_CNTL_17_P2               (1L<<28)
3408 #define BNX2_RPM_RC_CNTL_17_P3               (1L<<29)
3409 #define BNX2_RPM_RC_CNTL_17_NBIT             (1L<<30)
3410 
3411 #define BNX2_RPM_RC_VALUE_MASK_17           0x000018ec
3412 #define BNX2_RPM_RC_VALUE_MASK_17_VALUE          (0xffffL<<0)
3413 #define BNX2_RPM_RC_VALUE_MASK_17_MASK           (0xffffL<<16)
3414 
3415 #define BNX2_RPM_RC_CNTL_18             0x000018f0
3416 #define BNX2_RPM_RC_CNTL_18_OFFSET           (0xffL<<0)
3417 #define BNX2_RPM_RC_CNTL_18_CLASS            (0x7L<<8)
3418 #define BNX2_RPM_RC_CNTL_18_PRIORITY             (1L<<11)
3419 #define BNX2_RPM_RC_CNTL_18_P4               (1L<<12)
3420 #define BNX2_RPM_RC_CNTL_18_HDR_TYPE             (0x7L<<13)
3421 #define BNX2_RPM_RC_CNTL_18_HDR_TYPE_START       (0L<<13)
3422 #define BNX2_RPM_RC_CNTL_18_HDR_TYPE_IP          (1L<<13)
3423 #define BNX2_RPM_RC_CNTL_18_HDR_TYPE_TCP         (2L<<13)
3424 #define BNX2_RPM_RC_CNTL_18_HDR_TYPE_UDP         (3L<<13)
3425 #define BNX2_RPM_RC_CNTL_18_HDR_TYPE_DATA        (4L<<13)
3426 #define BNX2_RPM_RC_CNTL_18_HDR_TYPE_TCP_UDP         (5L<<13)
3427 #define BNX2_RPM_RC_CNTL_18_HDR_TYPE_ICMPV6      (6L<<13)
3428 #define BNX2_RPM_RC_CNTL_18_COMP             (0x3L<<16)
3429 #define BNX2_RPM_RC_CNTL_18_COMP_EQUAL           (0L<<16)
3430 #define BNX2_RPM_RC_CNTL_18_COMP_NEQUAL          (1L<<16)
3431 #define BNX2_RPM_RC_CNTL_18_COMP_GREATER         (2L<<16)
3432 #define BNX2_RPM_RC_CNTL_18_COMP_LESS            (3L<<16)
3433 #define BNX2_RPM_RC_CNTL_18_MAP              (1L<<18)
3434 #define BNX2_RPM_RC_CNTL_18_SBIT             (1L<<19)
3435 #define BNX2_RPM_RC_CNTL_18_CMDSEL           (0x1fL<<20)
3436 #define BNX2_RPM_RC_CNTL_18_DISCARD          (1L<<25)
3437 #define BNX2_RPM_RC_CNTL_18_MASK             (1L<<26)
3438 #define BNX2_RPM_RC_CNTL_18_P1               (1L<<27)
3439 #define BNX2_RPM_RC_CNTL_18_P2               (1L<<28)
3440 #define BNX2_RPM_RC_CNTL_18_P3               (1L<<29)
3441 #define BNX2_RPM_RC_CNTL_18_NBIT             (1L<<30)
3442 
3443 #define BNX2_RPM_RC_VALUE_MASK_18           0x000018f4
3444 #define BNX2_RPM_RC_VALUE_MASK_18_VALUE          (0xffffL<<0)
3445 #define BNX2_RPM_RC_VALUE_MASK_18_MASK           (0xffffL<<16)
3446 
3447 #define BNX2_RPM_RC_CNTL_19             0x000018f8
3448 #define BNX2_RPM_RC_CNTL_19_OFFSET           (0xffL<<0)
3449 #define BNX2_RPM_RC_CNTL_19_CLASS            (0x7L<<8)
3450 #define BNX2_RPM_RC_CNTL_19_PRIORITY             (1L<<11)
3451 #define BNX2_RPM_RC_CNTL_19_P4               (1L<<12)
3452 #define BNX2_RPM_RC_CNTL_19_HDR_TYPE             (0x7L<<13)
3453 #define BNX2_RPM_RC_CNTL_19_HDR_TYPE_START       (0L<<13)
3454 #define BNX2_RPM_RC_CNTL_19_HDR_TYPE_IP          (1L<<13)
3455 #define BNX2_RPM_RC_CNTL_19_HDR_TYPE_TCP         (2L<<13)
3456 #define BNX2_RPM_RC_CNTL_19_HDR_TYPE_UDP         (3L<<13)
3457 #define BNX2_RPM_RC_CNTL_19_HDR_TYPE_DATA        (4L<<13)
3458 #define BNX2_RPM_RC_CNTL_19_HDR_TYPE_TCP_UDP         (5L<<13)
3459 #define BNX2_RPM_RC_CNTL_19_HDR_TYPE_ICMPV6      (6L<<13)
3460 #define BNX2_RPM_RC_CNTL_19_COMP             (0x3L<<16)
3461 #define BNX2_RPM_RC_CNTL_19_COMP_EQUAL           (0L<<16)
3462 #define BNX2_RPM_RC_CNTL_19_COMP_NEQUAL          (1L<<16)
3463 #define BNX2_RPM_RC_CNTL_19_COMP_GREATER         (2L<<16)
3464 #define BNX2_RPM_RC_CNTL_19_COMP_LESS            (3L<<16)
3465 #define BNX2_RPM_RC_CNTL_19_MAP              (1L<<18)
3466 #define BNX2_RPM_RC_CNTL_19_SBIT             (1L<<19)
3467 #define BNX2_RPM_RC_CNTL_19_CMDSEL           (0x1fL<<20)
3468 #define BNX2_RPM_RC_CNTL_19_DISCARD          (1L<<25)
3469 #define BNX2_RPM_RC_CNTL_19_MASK             (1L<<26)
3470 #define BNX2_RPM_RC_CNTL_19_P1               (1L<<27)
3471 #define BNX2_RPM_RC_CNTL_19_P2               (1L<<28)
3472 #define BNX2_RPM_RC_CNTL_19_P3               (1L<<29)
3473 #define BNX2_RPM_RC_CNTL_19_NBIT             (1L<<30)
3474 
3475 #define BNX2_RPM_RC_VALUE_MASK_19           0x000018fc
3476 #define BNX2_RPM_RC_VALUE_MASK_19_VALUE          (0xffffL<<0)
3477 #define BNX2_RPM_RC_VALUE_MASK_19_MASK           (0xffffL<<16)
3478 
3479 #define BNX2_RPM_RC_CNTL_0              0x00001900
3480 #define BNX2_RPM_RC_CNTL_0_OFFSET            (0xffL<<0)
3481 #define BNX2_RPM_RC_CNTL_0_CLASS             (0x7L<<8)
3482 #define BNX2_RPM_RC_CNTL_0_PRIORITY          (1L<<11)
3483 #define BNX2_RPM_RC_CNTL_0_P4                (1L<<12)
3484 #define BNX2_RPM_RC_CNTL_0_HDR_TYPE          (0x7L<<13)
3485 #define BNX2_RPM_RC_CNTL_0_HDR_TYPE_START        (0L<<13)
3486 #define BNX2_RPM_RC_CNTL_0_HDR_TYPE_IP           (1L<<13)
3487 #define BNX2_RPM_RC_CNTL_0_HDR_TYPE_TCP          (2L<<13)
3488 #define BNX2_RPM_RC_CNTL_0_HDR_TYPE_UDP          (3L<<13)
3489 #define BNX2_RPM_RC_CNTL_0_HDR_TYPE_DATA         (4L<<13)
3490 #define BNX2_RPM_RC_CNTL_0_HDR_TYPE_TCP_UDP      (5L<<13)
3491 #define BNX2_RPM_RC_CNTL_0_HDR_TYPE_ICMPV6       (6L<<13)
3492 #define BNX2_RPM_RC_CNTL_0_COMP              (0x3L<<16)
3493 #define BNX2_RPM_RC_CNTL_0_COMP_EQUAL            (0L<<16)
3494 #define BNX2_RPM_RC_CNTL_0_COMP_NEQUAL           (1L<<16)
3495 #define BNX2_RPM_RC_CNTL_0_COMP_GREATER          (2L<<16)
3496 #define BNX2_RPM_RC_CNTL_0_COMP_LESS             (3L<<16)
3497 #define BNX2_RPM_RC_CNTL_0_MAP_XI            (1L<<18)
3498 #define BNX2_RPM_RC_CNTL_0_SBIT              (1L<<19)
3499 #define BNX2_RPM_RC_CNTL_0_CMDSEL            (0xfL<<20)
3500 #define BNX2_RPM_RC_CNTL_0_MAP               (1L<<24)
3501 #define BNX2_RPM_RC_CNTL_0_CMDSEL_XI             (0x1fL<<20)
3502 #define BNX2_RPM_RC_CNTL_0_DISCARD           (1L<<25)
3503 #define BNX2_RPM_RC_CNTL_0_MASK              (1L<<26)
3504 #define BNX2_RPM_RC_CNTL_0_P1                (1L<<27)
3505 #define BNX2_RPM_RC_CNTL_0_P2                (1L<<28)
3506 #define BNX2_RPM_RC_CNTL_0_P3                (1L<<29)
3507 #define BNX2_RPM_RC_CNTL_0_NBIT              (1L<<30)
3508 
3509 #define BNX2_RPM_RC_VALUE_MASK_0            0x00001904
3510 #define BNX2_RPM_RC_VALUE_MASK_0_VALUE           (0xffffL<<0)
3511 #define BNX2_RPM_RC_VALUE_MASK_0_MASK            (0xffffL<<16)
3512 
3513 #define BNX2_RPM_RC_CNTL_1              0x00001908
3514 #define BNX2_RPM_RC_CNTL_1_A                 (0x3ffffL<<0)
3515 #define BNX2_RPM_RC_CNTL_1_B                 (0xfffL<<19)
3516 #define BNX2_RPM_RC_CNTL_1_OFFSET_XI             (0xffL<<0)
3517 #define BNX2_RPM_RC_CNTL_1_CLASS_XI          (0x7L<<8)
3518 #define BNX2_RPM_RC_CNTL_1_PRIORITY_XI           (1L<<11)
3519 #define BNX2_RPM_RC_CNTL_1_P4_XI             (1L<<12)
3520 #define BNX2_RPM_RC_CNTL_1_HDR_TYPE_XI           (0x7L<<13)
3521 #define BNX2_RPM_RC_CNTL_1_HDR_TYPE_START_XI         (0L<<13)
3522 #define BNX2_RPM_RC_CNTL_1_HDR_TYPE_IP_XI        (1L<<13)
3523 #define BNX2_RPM_RC_CNTL_1_HDR_TYPE_TCP_XI       (2L<<13)
3524 #define BNX2_RPM_RC_CNTL_1_HDR_TYPE_UDP_XI       (3L<<13)
3525 #define BNX2_RPM_RC_CNTL_1_HDR_TYPE_DATA_XI      (4L<<13)
3526 #define BNX2_RPM_RC_CNTL_1_HDR_TYPE_TCP_UDP_XI       (5L<<13)
3527 #define BNX2_RPM_RC_CNTL_1_HDR_TYPE_ICMPV6_XI        (6L<<13)
3528 #define BNX2_RPM_RC_CNTL_1_COMP_XI           (0x3L<<16)
3529 #define BNX2_RPM_RC_CNTL_1_COMP_EQUAL_XI         (0L<<16)
3530 #define BNX2_RPM_RC_CNTL_1_COMP_NEQUAL_XI        (1L<<16)
3531 #define BNX2_RPM_RC_CNTL_1_COMP_GREATER_XI       (2L<<16)
3532 #define BNX2_RPM_RC_CNTL_1_COMP_LESS_XI          (3L<<16)
3533 #define BNX2_RPM_RC_CNTL_1_MAP_XI            (1L<<18)
3534 #define BNX2_RPM_RC_CNTL_1_SBIT_XI           (1L<<19)
3535 #define BNX2_RPM_RC_CNTL_1_CMDSEL_XI             (0x1fL<<20)
3536 #define BNX2_RPM_RC_CNTL_1_DISCARD_XI            (1L<<25)
3537 #define BNX2_RPM_RC_CNTL_1_MASK_XI           (1L<<26)
3538 #define BNX2_RPM_RC_CNTL_1_P1_XI             (1L<<27)
3539 #define BNX2_RPM_RC_CNTL_1_P2_XI             (1L<<28)
3540 #define BNX2_RPM_RC_CNTL_1_P3_XI             (1L<<29)
3541 #define BNX2_RPM_RC_CNTL_1_NBIT_XI           (1L<<30)
3542 
3543 #define BNX2_RPM_RC_VALUE_MASK_1            0x0000190c
3544 #define BNX2_RPM_RC_VALUE_MASK_1_VALUE           (0xffffL<<0)
3545 #define BNX2_RPM_RC_VALUE_MASK_1_MASK            (0xffffL<<16)
3546 
3547 #define BNX2_RPM_RC_CNTL_2              0x00001910
3548 #define BNX2_RPM_RC_CNTL_2_A                 (0x3ffffL<<0)
3549 #define BNX2_RPM_RC_CNTL_2_B                 (0xfffL<<19)
3550 #define BNX2_RPM_RC_CNTL_2_OFFSET_XI             (0xffL<<0)
3551 #define BNX2_RPM_RC_CNTL_2_CLASS_XI          (0x7L<<8)
3552 #define BNX2_RPM_RC_CNTL_2_PRIORITY_XI           (1L<<11)
3553 #define BNX2_RPM_RC_CNTL_2_P4_XI             (1L<<12)
3554 #define BNX2_RPM_RC_CNTL_2_HDR_TYPE_XI           (0x7L<<13)
3555 #define BNX2_RPM_RC_CNTL_2_HDR_TYPE_START_XI         (0L<<13)
3556 #define BNX2_RPM_RC_CNTL_2_HDR_TYPE_IP_XI        (1L<<13)
3557 #define BNX2_RPM_RC_CNTL_2_HDR_TYPE_TCP_XI       (2L<<13)
3558 #define BNX2_RPM_RC_CNTL_2_HDR_TYPE_UDP_XI       (3L<<13)
3559 #define BNX2_RPM_RC_CNTL_2_HDR_TYPE_DATA_XI      (4L<<13)
3560 #define BNX2_RPM_RC_CNTL_2_HDR_TYPE_TCP_UDP_XI       (5L<<13)
3561 #define BNX2_RPM_RC_CNTL_2_HDR_TYPE_ICMPV6_XI        (6L<<13)
3562 #define BNX2_RPM_RC_CNTL_2_COMP_XI           (0x3L<<16)
3563 #define BNX2_RPM_RC_CNTL_2_COMP_EQUAL_XI         (0L<<16)
3564 #define BNX2_RPM_RC_CNTL_2_COMP_NEQUAL_XI        (1L<<16)
3565 #define BNX2_RPM_RC_CNTL_2_COMP_GREATER_XI       (2L<<16)
3566 #define BNX2_RPM_RC_CNTL_2_COMP_LESS_XI          (3L<<16)
3567 #define BNX2_RPM_RC_CNTL_2_MAP_XI            (1L<<18)
3568 #define BNX2_RPM_RC_CNTL_2_SBIT_XI           (1L<<19)
3569 #define BNX2_RPM_RC_CNTL_2_CMDSEL_XI             (0x1fL<<20)
3570 #define BNX2_RPM_RC_CNTL_2_DISCARD_XI            (1L<<25)
3571 #define BNX2_RPM_RC_CNTL_2_MASK_XI           (1L<<26)
3572 #define BNX2_RPM_RC_CNTL_2_P1_XI             (1L<<27)
3573 #define BNX2_RPM_RC_CNTL_2_P2_XI             (1L<<28)
3574 #define BNX2_RPM_RC_CNTL_2_P3_XI             (1L<<29)
3575 #define BNX2_RPM_RC_CNTL_2_NBIT_XI           (1L<<30)
3576 
3577 #define BNX2_RPM_RC_VALUE_MASK_2            0x00001914
3578 #define BNX2_RPM_RC_VALUE_MASK_2_VALUE           (0xffffL<<0)
3579 #define BNX2_RPM_RC_VALUE_MASK_2_MASK            (0xffffL<<16)
3580 
3581 #define BNX2_RPM_RC_CNTL_3              0x00001918
3582 #define BNX2_RPM_RC_CNTL_3_A                 (0x3ffffL<<0)
3583 #define BNX2_RPM_RC_CNTL_3_B                 (0xfffL<<19)
3584 #define BNX2_RPM_RC_CNTL_3_OFFSET_XI             (0xffL<<0)
3585 #define BNX2_RPM_RC_CNTL_3_CLASS_XI          (0x7L<<8)
3586 #define BNX2_RPM_RC_CNTL_3_PRIORITY_XI           (1L<<11)
3587 #define BNX2_RPM_RC_CNTL_3_P4_XI             (1L<<12)
3588 #define BNX2_RPM_RC_CNTL_3_HDR_TYPE_XI           (0x7L<<13)
3589 #define BNX2_RPM_RC_CNTL_3_HDR_TYPE_START_XI         (0L<<13)
3590 #define BNX2_RPM_RC_CNTL_3_HDR_TYPE_IP_XI        (1L<<13)
3591 #define BNX2_RPM_RC_CNTL_3_HDR_TYPE_TCP_XI       (2L<<13)
3592 #define BNX2_RPM_RC_CNTL_3_HDR_TYPE_UDP_XI       (3L<<13)
3593 #define BNX2_RPM_RC_CNTL_3_HDR_TYPE_DATA_XI      (4L<<13)
3594 #define BNX2_RPM_RC_CNTL_3_HDR_TYPE_TCP_UDP_XI       (5L<<13)
3595 #define BNX2_RPM_RC_CNTL_3_HDR_TYPE_ICMPV6_XI        (6L<<13)
3596 #define BNX2_RPM_RC_CNTL_3_COMP_XI           (0x3L<<16)
3597 #define BNX2_RPM_RC_CNTL_3_COMP_EQUAL_XI         (0L<<16)
3598 #define BNX2_RPM_RC_CNTL_3_COMP_NEQUAL_XI        (1L<<16)
3599 #define BNX2_RPM_RC_CNTL_3_COMP_GREATER_XI       (2L<<16)
3600 #define BNX2_RPM_RC_CNTL_3_COMP_LESS_XI          (3L<<16)
3601 #define BNX2_RPM_RC_CNTL_3_MAP_XI            (1L<<18)
3602 #define BNX2_RPM_RC_CNTL_3_SBIT_XI           (1L<<19)
3603 #define BNX2_RPM_RC_CNTL_3_CMDSEL_XI             (0x1fL<<20)
3604 #define BNX2_RPM_RC_CNTL_3_DISCARD_XI            (1L<<25)
3605 #define BNX2_RPM_RC_CNTL_3_MASK_XI           (1L<<26)
3606 #define BNX2_RPM_RC_CNTL_3_P1_XI             (1L<<27)
3607 #define BNX2_RPM_RC_CNTL_3_P2_XI             (1L<<28)
3608 #define BNX2_RPM_RC_CNTL_3_P3_XI             (1L<<29)
3609 #define BNX2_RPM_RC_CNTL_3_NBIT_XI           (1L<<30)
3610 
3611 #define BNX2_RPM_RC_VALUE_MASK_3            0x0000191c
3612 #define BNX2_RPM_RC_VALUE_MASK_3_VALUE           (0xffffL<<0)
3613 #define BNX2_RPM_RC_VALUE_MASK_3_MASK            (0xffffL<<16)
3614 
3615 #define BNX2_RPM_RC_CNTL_4              0x00001920
3616 #define BNX2_RPM_RC_CNTL_4_A                 (0x3ffffL<<0)
3617 #define BNX2_RPM_RC_CNTL_4_B                 (0xfffL<<19)
3618 #define BNX2_RPM_RC_CNTL_4_OFFSET_XI             (0xffL<<0)
3619 #define BNX2_RPM_RC_CNTL_4_CLASS_XI          (0x7L<<8)
3620 #define BNX2_RPM_RC_CNTL_4_PRIORITY_XI           (1L<<11)
3621 #define BNX2_RPM_RC_CNTL_4_P4_XI             (1L<<12)
3622 #define BNX2_RPM_RC_CNTL_4_HDR_TYPE_XI           (0x7L<<13)
3623 #define BNX2_RPM_RC_CNTL_4_HDR_TYPE_START_XI         (0L<<13)
3624 #define BNX2_RPM_RC_CNTL_4_HDR_TYPE_IP_XI        (1L<<13)
3625 #define BNX2_RPM_RC_CNTL_4_HDR_TYPE_TCP_XI       (2L<<13)
3626 #define BNX2_RPM_RC_CNTL_4_HDR_TYPE_UDP_XI       (3L<<13)
3627 #define BNX2_RPM_RC_CNTL_4_HDR_TYPE_DATA_XI      (4L<<13)
3628 #define BNX2_RPM_RC_CNTL_4_HDR_TYPE_TCP_UDP_XI       (5L<<13)
3629 #define BNX2_RPM_RC_CNTL_4_HDR_TYPE_ICMPV6_XI        (6L<<13)
3630 #define BNX2_RPM_RC_CNTL_4_COMP_XI           (0x3L<<16)
3631 #define BNX2_RPM_RC_CNTL_4_COMP_EQUAL_XI         (0L<<16)
3632 #define BNX2_RPM_RC_CNTL_4_COMP_NEQUAL_XI        (1L<<16)
3633 #define BNX2_RPM_RC_CNTL_4_COMP_GREATER_XI       (2L<<16)
3634 #define BNX2_RPM_RC_CNTL_4_COMP_LESS_XI          (3L<<16)
3635 #define BNX2_RPM_RC_CNTL_4_MAP_XI            (1L<<18)
3636 #define BNX2_RPM_RC_CNTL_4_SBIT_XI           (1L<<19)
3637 #define BNX2_RPM_RC_CNTL_4_CMDSEL_XI             (0x1fL<<20)
3638 #define BNX2_RPM_RC_CNTL_4_DISCARD_XI            (1L<<25)
3639 #define BNX2_RPM_RC_CNTL_4_MASK_XI           (1L<<26)
3640 #define BNX2_RPM_RC_CNTL_4_P1_XI             (1L<<27)
3641 #define BNX2_RPM_RC_CNTL_4_P2_XI             (1L<<28)
3642 #define BNX2_RPM_RC_CNTL_4_P3_XI             (1L<<29)
3643 #define BNX2_RPM_RC_CNTL_4_NBIT_XI           (1L<<30)
3644 
3645 #define BNX2_RPM_RC_VALUE_MASK_4            0x00001924
3646 #define BNX2_RPM_RC_VALUE_MASK_4_VALUE           (0xffffL<<0)
3647 #define BNX2_RPM_RC_VALUE_MASK_4_MASK            (0xffffL<<16)
3648 
3649 #define BNX2_RPM_RC_CNTL_5              0x00001928
3650 #define BNX2_RPM_RC_CNTL_5_A                 (0x3ffffL<<0)
3651 #define BNX2_RPM_RC_CNTL_5_B                 (0xfffL<<19)
3652 #define BNX2_RPM_RC_CNTL_5_OFFSET_XI             (0xffL<<0)
3653 #define BNX2_RPM_RC_CNTL_5_CLASS_XI          (0x7L<<8)
3654 #define BNX2_RPM_RC_CNTL_5_PRIORITY_XI           (1L<<11)
3655 #define BNX2_RPM_RC_CNTL_5_P4_XI             (1L<<12)
3656 #define BNX2_RPM_RC_CNTL_5_HDR_TYPE_XI           (0x7L<<13)
3657 #define BNX2_RPM_RC_CNTL_5_HDR_TYPE_START_XI         (0L<<13)
3658 #define BNX2_RPM_RC_CNTL_5_HDR_TYPE_IP_XI        (1L<<13)
3659 #define BNX2_RPM_RC_CNTL_5_HDR_TYPE_TCP_XI       (2L<<13)
3660 #define BNX2_RPM_RC_CNTL_5_HDR_TYPE_UDP_XI       (3L<<13)
3661 #define BNX2_RPM_RC_CNTL_5_HDR_TYPE_DATA_XI      (4L<<13)
3662 #define BNX2_RPM_RC_CNTL_5_HDR_TYPE_TCP_UDP_XI       (5L<<13)
3663 #define BNX2_RPM_RC_CNTL_5_HDR_TYPE_ICMPV6_XI        (6L<<13)
3664 #define BNX2_RPM_RC_CNTL_5_COMP_XI           (0x3L<<16)
3665 #define BNX2_RPM_RC_CNTL_5_COMP_EQUAL_XI         (0L<<16)
3666 #define BNX2_RPM_RC_CNTL_5_COMP_NEQUAL_XI        (1L<<16)
3667 #define BNX2_RPM_RC_CNTL_5_COMP_GREATER_XI       (2L<<16)
3668 #define BNX2_RPM_RC_CNTL_5_COMP_LESS_XI          (3L<<16)
3669 #define BNX2_RPM_RC_CNTL_5_MAP_XI            (1L<<18)
3670 #define BNX2_RPM_RC_CNTL_5_SBIT_XI           (1L<<19)
3671 #define BNX2_RPM_RC_CNTL_5_CMDSEL_XI             (0x1fL<<20)
3672 #define BNX2_RPM_RC_CNTL_5_DISCARD_XI            (1L<<25)
3673 #define BNX2_RPM_RC_CNTL_5_MASK_XI           (1L<<26)
3674 #define BNX2_RPM_RC_CNTL_5_P1_XI             (1L<<27)
3675 #define BNX2_RPM_RC_CNTL_5_P2_XI             (1L<<28)
3676 #define BNX2_RPM_RC_CNTL_5_P3_XI             (1L<<29)
3677 #define BNX2_RPM_RC_CNTL_5_NBIT_XI           (1L<<30)
3678 
3679 #define BNX2_RPM_RC_VALUE_MASK_5            0x0000192c
3680 #define BNX2_RPM_RC_VALUE_MASK_5_VALUE           (0xffffL<<0)
3681 #define BNX2_RPM_RC_VALUE_MASK_5_MASK            (0xffffL<<16)
3682 
3683 #define BNX2_RPM_RC_CNTL_6              0x00001930
3684 #define BNX2_RPM_RC_CNTL_6_A                 (0x3ffffL<<0)
3685 #define BNX2_RPM_RC_CNTL_6_B                 (0xfffL<<19)
3686 #define BNX2_RPM_RC_CNTL_6_OFFSET_XI             (0xffL<<0)
3687 #define BNX2_RPM_RC_CNTL_6_CLASS_XI          (0x7L<<8)
3688 #define BNX2_RPM_RC_CNTL_6_PRIORITY_XI           (1L<<11)
3689 #define BNX2_RPM_RC_CNTL_6_P4_XI             (1L<<12)
3690 #define BNX2_RPM_RC_CNTL_6_HDR_TYPE_XI           (0x7L<<13)
3691 #define BNX2_RPM_RC_CNTL_6_HDR_TYPE_START_XI         (0L<<13)
3692 #define BNX2_RPM_RC_CNTL_6_HDR_TYPE_IP_XI        (1L<<13)
3693 #define BNX2_RPM_RC_CNTL_6_HDR_TYPE_TCP_XI       (2L<<13)
3694 #define BNX2_RPM_RC_CNTL_6_HDR_TYPE_UDP_XI       (3L<<13)
3695 #define BNX2_RPM_RC_CNTL_6_HDR_TYPE_DATA_XI      (4L<<13)
3696 #define BNX2_RPM_RC_CNTL_6_HDR_TYPE_TCP_UDP_XI       (5L<<13)
3697 #define BNX2_RPM_RC_CNTL_6_HDR_TYPE_ICMPV6_XI        (6L<<13)
3698 #define BNX2_RPM_RC_CNTL_6_COMP_XI           (0x3L<<16)
3699 #define BNX2_RPM_RC_CNTL_6_COMP_EQUAL_XI         (0L<<16)
3700 #define BNX2_RPM_RC_CNTL_6_COMP_NEQUAL_XI        (1L<<16)
3701 #define BNX2_RPM_RC_CNTL_6_COMP_GREATER_XI       (2L<<16)
3702 #define BNX2_RPM_RC_CNTL_6_COMP_LESS_XI          (3L<<16)
3703 #define BNX2_RPM_RC_CNTL_6_MAP_XI            (1L<<18)
3704 #define BNX2_RPM_RC_CNTL_6_SBIT_XI           (1L<<19)
3705 #define BNX2_RPM_RC_CNTL_6_CMDSEL_XI             (0x1fL<<20)
3706 #define BNX2_RPM_RC_CNTL_6_DISCARD_XI            (1L<<25)
3707 #define BNX2_RPM_RC_CNTL_6_MASK_XI           (1L<<26)
3708 #define BNX2_RPM_RC_CNTL_6_P1_XI             (1L<<27)
3709 #define BNX2_RPM_RC_CNTL_6_P2_XI             (1L<<28)
3710 #define BNX2_RPM_RC_CNTL_6_P3_XI             (1L<<29)
3711 #define BNX2_RPM_RC_CNTL_6_NBIT_XI           (1L<<30)
3712 
3713 #define BNX2_RPM_RC_VALUE_MASK_6            0x00001934
3714 #define BNX2_RPM_RC_VALUE_MASK_6_VALUE           (0xffffL<<0)
3715 #define BNX2_RPM_RC_VALUE_MASK_6_MASK            (0xffffL<<16)
3716 
3717 #define BNX2_RPM_RC_CNTL_7              0x00001938
3718 #define BNX2_RPM_RC_CNTL_7_A                 (0x3ffffL<<0)
3719 #define BNX2_RPM_RC_CNTL_7_B                 (0xfffL<<19)
3720 #define BNX2_RPM_RC_CNTL_7_OFFSET_XI             (0xffL<<0)
3721 #define BNX2_RPM_RC_CNTL_7_CLASS_XI          (0x7L<<8)
3722 #define BNX2_RPM_RC_CNTL_7_PRIORITY_XI           (1L<<11)
3723 #define BNX2_RPM_RC_CNTL_7_P4_XI             (1L<<12)
3724 #define BNX2_RPM_RC_CNTL_7_HDR_TYPE_XI           (0x7L<<13)
3725 #define BNX2_RPM_RC_CNTL_7_HDR_TYPE_START_XI         (0L<<13)
3726 #define BNX2_RPM_RC_CNTL_7_HDR_TYPE_IP_XI        (1L<<13)
3727 #define BNX2_RPM_RC_CNTL_7_HDR_TYPE_TCP_XI       (2L<<13)
3728 #define BNX2_RPM_RC_CNTL_7_HDR_TYPE_UDP_XI       (3L<<13)
3729 #define BNX2_RPM_RC_CNTL_7_HDR_TYPE_DATA_XI      (4L<<13)
3730 #define BNX2_RPM_RC_CNTL_7_HDR_TYPE_TCP_UDP_XI       (5L<<13)
3731 #define BNX2_RPM_RC_CNTL_7_HDR_TYPE_ICMPV6_XI        (6L<<13)
3732 #define BNX2_RPM_RC_CNTL_7_COMP_XI           (0x3L<<16)
3733 #define BNX2_RPM_RC_CNTL_7_COMP_EQUAL_XI         (0L<<16)
3734 #define BNX2_RPM_RC_CNTL_7_COMP_NEQUAL_XI        (1L<<16)
3735 #define BNX2_RPM_RC_CNTL_7_COMP_GREATER_XI       (2L<<16)
3736 #define BNX2_RPM_RC_CNTL_7_COMP_LESS_XI          (3L<<16)
3737 #define BNX2_RPM_RC_CNTL_7_MAP_XI            (1L<<18)
3738 #define BNX2_RPM_RC_CNTL_7_SBIT_XI           (1L<<19)
3739 #define BNX2_RPM_RC_CNTL_7_CMDSEL_XI             (0x1fL<<20)
3740 #define BNX2_RPM_RC_CNTL_7_DISCARD_XI            (1L<<25)
3741 #define BNX2_RPM_RC_CNTL_7_MASK_XI           (1L<<26)
3742 #define BNX2_RPM_RC_CNTL_7_P1_XI             (1L<<27)
3743 #define BNX2_RPM_RC_CNTL_7_P2_XI             (1L<<28)
3744 #define BNX2_RPM_RC_CNTL_7_P3_XI             (1L<<29)
3745 #define BNX2_RPM_RC_CNTL_7_NBIT_XI           (1L<<30)
3746 
3747 #define BNX2_RPM_RC_VALUE_MASK_7            0x0000193c
3748 #define BNX2_RPM_RC_VALUE_MASK_7_VALUE           (0xffffL<<0)
3749 #define BNX2_RPM_RC_VALUE_MASK_7_MASK            (0xffffL<<16)
3750 
3751 #define BNX2_RPM_RC_CNTL_8              0x00001940
3752 #define BNX2_RPM_RC_CNTL_8_A                 (0x3ffffL<<0)
3753 #define BNX2_RPM_RC_CNTL_8_B                 (0xfffL<<19)
3754 #define BNX2_RPM_RC_CNTL_8_OFFSET_XI             (0xffL<<0)
3755 #define BNX2_RPM_RC_CNTL_8_CLASS_XI          (0x7L<<8)
3756 #define BNX2_RPM_RC_CNTL_8_PRIORITY_XI           (1L<<11)
3757 #define BNX2_RPM_RC_CNTL_8_P4_XI             (1L<<12)
3758 #define BNX2_RPM_RC_CNTL_8_HDR_TYPE_XI           (0x7L<<13)
3759 #define BNX2_RPM_RC_CNTL_8_HDR_TYPE_START_XI         (0L<<13)
3760 #define BNX2_RPM_RC_CNTL_8_HDR_TYPE_IP_XI        (1L<<13)
3761 #define BNX2_RPM_RC_CNTL_8_HDR_TYPE_TCP_XI       (2L<<13)
3762 #define BNX2_RPM_RC_CNTL_8_HDR_TYPE_UDP_XI       (3L<<13)
3763 #define BNX2_RPM_RC_CNTL_8_HDR_TYPE_DATA_XI      (4L<<13)
3764 #define BNX2_RPM_RC_CNTL_8_HDR_TYPE_TCP_UDP_XI       (5L<<13)
3765 #define BNX2_RPM_RC_CNTL_8_HDR_TYPE_ICMPV6_XI        (6L<<13)
3766 #define BNX2_RPM_RC_CNTL_8_COMP_XI           (0x3L<<16)
3767 #define BNX2_RPM_RC_CNTL_8_COMP_EQUAL_XI         (0L<<16)
3768 #define BNX2_RPM_RC_CNTL_8_COMP_NEQUAL_XI        (1L<<16)
3769 #define BNX2_RPM_RC_CNTL_8_COMP_GREATER_XI       (2L<<16)
3770 #define BNX2_RPM_RC_CNTL_8_COMP_LESS_XI          (3L<<16)
3771 #define BNX2_RPM_RC_CNTL_8_MAP_XI            (1L<<18)
3772 #define BNX2_RPM_RC_CNTL_8_SBIT_XI           (1L<<19)
3773 #define BNX2_RPM_RC_CNTL_8_CMDSEL_XI             (0x1fL<<20)
3774 #define BNX2_RPM_RC_CNTL_8_DISCARD_XI            (1L<<25)
3775 #define BNX2_RPM_RC_CNTL_8_MASK_XI           (1L<<26)
3776 #define BNX2_RPM_RC_CNTL_8_P1_XI             (1L<<27)
3777 #define BNX2_RPM_RC_CNTL_8_P2_XI             (1L<<28)
3778 #define BNX2_RPM_RC_CNTL_8_P3_XI             (1L<<29)
3779 #define BNX2_RPM_RC_CNTL_8_NBIT_XI           (1L<<30)
3780 
3781 #define BNX2_RPM_RC_VALUE_MASK_8            0x00001944
3782 #define BNX2_RPM_RC_VALUE_MASK_8_VALUE           (0xffffL<<0)
3783 #define BNX2_RPM_RC_VALUE_MASK_8_MASK            (0xffffL<<16)
3784 
3785 #define BNX2_RPM_RC_CNTL_9              0x00001948
3786 #define BNX2_RPM_RC_CNTL_9_A                 (0x3ffffL<<0)
3787 #define BNX2_RPM_RC_CNTL_9_B                 (0xfffL<<19)
3788 #define BNX2_RPM_RC_CNTL_9_OFFSET_XI             (0xffL<<0)
3789 #define BNX2_RPM_RC_CNTL_9_CLASS_XI          (0x7L<<8)
3790 #define BNX2_RPM_RC_CNTL_9_PRIORITY_XI           (1L<<11)
3791 #define BNX2_RPM_RC_CNTL_9_P4_XI             (1L<<12)
3792 #define BNX2_RPM_RC_CNTL_9_HDR_TYPE_XI           (0x7L<<13)
3793 #define BNX2_RPM_RC_CNTL_9_HDR_TYPE_START_XI         (0L<<13)
3794 #define BNX2_RPM_RC_CNTL_9_HDR_TYPE_IP_XI        (1L<<13)
3795 #define BNX2_RPM_RC_CNTL_9_HDR_TYPE_TCP_XI       (2L<<13)
3796 #define BNX2_RPM_RC_CNTL_9_HDR_TYPE_UDP_XI       (3L<<13)
3797 #define BNX2_RPM_RC_CNTL_9_HDR_TYPE_DATA_XI      (4L<<13)
3798 #define BNX2_RPM_RC_CNTL_9_HDR_TYPE_TCP_UDP_XI       (5L<<13)
3799 #define BNX2_RPM_RC_CNTL_9_HDR_TYPE_ICMPV6_XI        (6L<<13)
3800 #define BNX2_RPM_RC_CNTL_9_COMP_XI           (0x3L<<16)
3801 #define BNX2_RPM_RC_CNTL_9_COMP_EQUAL_XI         (0L<<16)
3802 #define BNX2_RPM_RC_CNTL_9_COMP_NEQUAL_XI        (1L<<16)
3803 #define BNX2_RPM_RC_CNTL_9_COMP_GREATER_XI       (2L<<16)
3804 #define BNX2_RPM_RC_CNTL_9_COMP_LESS_XI          (3L<<16)
3805 #define BNX2_RPM_RC_CNTL_9_MAP_XI            (1L<<18)
3806 #define BNX2_RPM_RC_CNTL_9_SBIT_XI           (1L<<19)
3807 #define BNX2_RPM_RC_CNTL_9_CMDSEL_XI             (0x1fL<<20)
3808 #define BNX2_RPM_RC_CNTL_9_DISCARD_XI            (1L<<25)
3809 #define BNX2_RPM_RC_CNTL_9_MASK_XI           (1L<<26)
3810 #define BNX2_RPM_RC_CNTL_9_P1_XI             (1L<<27)
3811 #define BNX2_RPM_RC_CNTL_9_P2_XI             (1L<<28)
3812 #define BNX2_RPM_RC_CNTL_9_P3_XI             (1L<<29)
3813 #define BNX2_RPM_RC_CNTL_9_NBIT_XI           (1L<<30)
3814 
3815 #define BNX2_RPM_RC_VALUE_MASK_9            0x0000194c
3816 #define BNX2_RPM_RC_VALUE_MASK_9_VALUE           (0xffffL<<0)
3817 #define BNX2_RPM_RC_VALUE_MASK_9_MASK            (0xffffL<<16)
3818 
3819 #define BNX2_RPM_RC_CNTL_10             0x00001950
3820 #define BNX2_RPM_RC_CNTL_10_A                (0x3ffffL<<0)
3821 #define BNX2_RPM_RC_CNTL_10_B                (0xfffL<<19)
3822 #define BNX2_RPM_RC_CNTL_10_OFFSET_XI            (0xffL<<0)
3823 #define BNX2_RPM_RC_CNTL_10_CLASS_XI             (0x7L<<8)
3824 #define BNX2_RPM_RC_CNTL_10_PRIORITY_XI          (1L<<11)
3825 #define BNX2_RPM_RC_CNTL_10_P4_XI            (1L<<12)
3826 #define BNX2_RPM_RC_CNTL_10_HDR_TYPE_XI          (0x7L<<13)
3827 #define BNX2_RPM_RC_CNTL_10_HDR_TYPE_START_XI        (0L<<13)
3828 #define BNX2_RPM_RC_CNTL_10_HDR_TYPE_IP_XI       (1L<<13)
3829 #define BNX2_RPM_RC_CNTL_10_HDR_TYPE_TCP_XI      (2L<<13)
3830 #define BNX2_RPM_RC_CNTL_10_HDR_TYPE_UDP_XI      (3L<<13)
3831 #define BNX2_RPM_RC_CNTL_10_HDR_TYPE_DATA_XI         (4L<<13)
3832 #define BNX2_RPM_RC_CNTL_10_HDR_TYPE_TCP_UDP_XI      (5L<<13)
3833 #define BNX2_RPM_RC_CNTL_10_HDR_TYPE_ICMPV6_XI       (6L<<13)
3834 #define BNX2_RPM_RC_CNTL_10_COMP_XI          (0x3L<<16)
3835 #define BNX2_RPM_RC_CNTL_10_COMP_EQUAL_XI        (0L<<16)
3836 #define BNX2_RPM_RC_CNTL_10_COMP_NEQUAL_XI       (1L<<16)
3837 #define BNX2_RPM_RC_CNTL_10_COMP_GREATER_XI      (2L<<16)
3838 #define BNX2_RPM_RC_CNTL_10_COMP_LESS_XI         (3L<<16)
3839 #define BNX2_RPM_RC_CNTL_10_MAP_XI           (1L<<18)
3840 #define BNX2_RPM_RC_CNTL_10_SBIT_XI          (1L<<19)
3841 #define BNX2_RPM_RC_CNTL_10_CMDSEL_XI            (0x1fL<<20)
3842 #define BNX2_RPM_RC_CNTL_10_DISCARD_XI           (1L<<25)
3843 #define BNX2_RPM_RC_CNTL_10_MASK_XI          (1L<<26)
3844 #define BNX2_RPM_RC_CNTL_10_P1_XI            (1L<<27)
3845 #define BNX2_RPM_RC_CNTL_10_P2_XI            (1L<<28)
3846 #define BNX2_RPM_RC_CNTL_10_P3_XI            (1L<<29)
3847 #define BNX2_RPM_RC_CNTL_10_NBIT_XI          (1L<<30)
3848 
3849 #define BNX2_RPM_RC_VALUE_MASK_10           0x00001954
3850 #define BNX2_RPM_RC_VALUE_MASK_10_VALUE          (0xffffL<<0)
3851 #define BNX2_RPM_RC_VALUE_MASK_10_MASK           (0xffffL<<16)
3852 
3853 #define BNX2_RPM_RC_CNTL_11             0x00001958
3854 #define BNX2_RPM_RC_CNTL_11_A                (0x3ffffL<<0)
3855 #define BNX2_RPM_RC_CNTL_11_B                (0xfffL<<19)
3856 #define BNX2_RPM_RC_CNTL_11_OFFSET_XI            (0xffL<<0)
3857 #define BNX2_RPM_RC_CNTL_11_CLASS_XI             (0x7L<<8)
3858 #define BNX2_RPM_RC_CNTL_11_PRIORITY_XI          (1L<<11)
3859 #define BNX2_RPM_RC_CNTL_11_P4_XI            (1L<<12)
3860 #define BNX2_RPM_RC_CNTL_11_HDR_TYPE_XI          (0x7L<<13)
3861 #define BNX2_RPM_RC_CNTL_11_HDR_TYPE_START_XI        (0L<<13)
3862 #define BNX2_RPM_RC_CNTL_11_HDR_TYPE_IP_XI       (1L<<13)
3863 #define BNX2_RPM_RC_CNTL_11_HDR_TYPE_TCP_XI      (2L<<13)
3864 #define BNX2_RPM_RC_CNTL_11_HDR_TYPE_UDP_XI      (3L<<13)
3865 #define BNX2_RPM_RC_CNTL_11_HDR_TYPE_DATA_XI         (4L<<13)
3866 #define BNX2_RPM_RC_CNTL_11_HDR_TYPE_TCP_UDP_XI      (5L<<13)
3867 #define BNX2_RPM_RC_CNTL_11_HDR_TYPE_ICMPV6_XI       (6L<<13)
3868 #define BNX2_RPM_RC_CNTL_11_COMP_XI          (0x3L<<16)
3869 #define BNX2_RPM_RC_CNTL_11_COMP_EQUAL_XI        (0L<<16)
3870 #define BNX2_RPM_RC_CNTL_11_COMP_NEQUAL_XI       (1L<<16)
3871 #define BNX2_RPM_RC_CNTL_11_COMP_GREATER_XI      (2L<<16)
3872 #define BNX2_RPM_RC_CNTL_11_COMP_LESS_XI         (3L<<16)
3873 #define BNX2_RPM_RC_CNTL_11_MAP_XI           (1L<<18)
3874 #define BNX2_RPM_RC_CNTL_11_SBIT_XI          (1L<<19)
3875 #define BNX2_RPM_RC_CNTL_11_CMDSEL_XI            (0x1fL<<20)
3876 #define BNX2_RPM_RC_CNTL_11_DISCARD_XI           (1L<<25)
3877 #define BNX2_RPM_RC_CNTL_11_MASK_XI          (1L<<26)
3878 #define BNX2_RPM_RC_CNTL_11_P1_XI            (1L<<27)
3879 #define BNX2_RPM_RC_CNTL_11_P2_XI            (1L<<28)
3880 #define BNX2_RPM_RC_CNTL_11_P3_XI            (1L<<29)
3881 #define BNX2_RPM_RC_CNTL_11_NBIT_XI          (1L<<30)
3882 
3883 #define BNX2_RPM_RC_VALUE_MASK_11           0x0000195c
3884 #define BNX2_RPM_RC_VALUE_MASK_11_VALUE          (0xffffL<<0)
3885 #define BNX2_RPM_RC_VALUE_MASK_11_MASK           (0xffffL<<16)
3886 
3887 #define BNX2_RPM_RC_CNTL_12             0x00001960
3888 #define BNX2_RPM_RC_CNTL_12_A                (0x3ffffL<<0)
3889 #define BNX2_RPM_RC_CNTL_12_B                (0xfffL<<19)
3890 #define BNX2_RPM_RC_CNTL_12_OFFSET_XI            (0xffL<<0)
3891 #define BNX2_RPM_RC_CNTL_12_CLASS_XI             (0x7L<<8)
3892 #define BNX2_RPM_RC_CNTL_12_PRIORITY_XI          (1L<<11)
3893 #define BNX2_RPM_RC_CNTL_12_P4_XI            (1L<<12)
3894 #define BNX2_RPM_RC_CNTL_12_HDR_TYPE_XI          (0x7L<<13)
3895 #define BNX2_RPM_RC_CNTL_12_HDR_TYPE_START_XI        (0L<<13)
3896 #define BNX2_RPM_RC_CNTL_12_HDR_TYPE_IP_XI       (1L<<13)
3897 #define BNX2_RPM_RC_CNTL_12_HDR_TYPE_TCP_XI      (2L<<13)
3898 #define BNX2_RPM_RC_CNTL_12_HDR_TYPE_UDP_XI      (3L<<13)
3899 #define BNX2_RPM_RC_CNTL_12_HDR_TYPE_DATA_XI         (4L<<13)
3900 #define BNX2_RPM_RC_CNTL_12_HDR_TYPE_TCP_UDP_XI      (5L<<13)
3901 #define BNX2_RPM_RC_CNTL_12_HDR_TYPE_ICMPV6_XI       (6L<<13)
3902 #define BNX2_RPM_RC_CNTL_12_COMP_XI          (0x3L<<16)
3903 #define BNX2_RPM_RC_CNTL_12_COMP_EQUAL_XI        (0L<<16)
3904 #define BNX2_RPM_RC_CNTL_12_COMP_NEQUAL_XI       (1L<<16)
3905 #define BNX2_RPM_RC_CNTL_12_COMP_GREATER_XI      (2L<<16)
3906 #define BNX2_RPM_RC_CNTL_12_COMP_LESS_XI         (3L<<16)
3907 #define BNX2_RPM_RC_CNTL_12_MAP_XI           (1L<<18)
3908 #define BNX2_RPM_RC_CNTL_12_SBIT_XI          (1L<<19)
3909 #define BNX2_RPM_RC_CNTL_12_CMDSEL_XI            (0x1fL<<20)
3910 #define BNX2_RPM_RC_CNTL_12_DISCARD_XI           (1L<<25)
3911 #define BNX2_RPM_RC_CNTL_12_MASK_XI          (1L<<26)
3912 #define BNX2_RPM_RC_CNTL_12_P1_XI            (1L<<27)
3913 #define BNX2_RPM_RC_CNTL_12_P2_XI            (1L<<28)
3914 #define BNX2_RPM_RC_CNTL_12_P3_XI            (1L<<29)
3915 #define BNX2_RPM_RC_CNTL_12_NBIT_XI          (1L<<30)
3916 
3917 #define BNX2_RPM_RC_VALUE_MASK_12           0x00001964
3918 #define BNX2_RPM_RC_VALUE_MASK_12_VALUE          (0xffffL<<0)
3919 #define BNX2_RPM_RC_VALUE_MASK_12_MASK           (0xffffL<<16)
3920 
3921 #define BNX2_RPM_RC_CNTL_13             0x00001968
3922 #define BNX2_RPM_RC_CNTL_13_A                (0x3ffffL<<0)
3923 #define BNX2_RPM_RC_CNTL_13_B                (0xfffL<<19)
3924 #define BNX2_RPM_RC_CNTL_13_OFFSET_XI            (0xffL<<0)
3925 #define BNX2_RPM_RC_CNTL_13_CLASS_XI             (0x7L<<8)
3926 #define BNX2_RPM_RC_CNTL_13_PRIORITY_XI          (1L<<11)
3927 #define BNX2_RPM_RC_CNTL_13_P4_XI            (1L<<12)
3928 #define BNX2_RPM_RC_CNTL_13_HDR_TYPE_XI          (0x7L<<13)
3929 #define BNX2_RPM_RC_CNTL_13_HDR_TYPE_START_XI        (0L<<13)
3930 #define BNX2_RPM_RC_CNTL_13_HDR_TYPE_IP_XI       (1L<<13)
3931 #define BNX2_RPM_RC_CNTL_13_HDR_TYPE_TCP_XI      (2L<<13)
3932 #define BNX2_RPM_RC_CNTL_13_HDR_TYPE_UDP_XI      (3L<<13)
3933 #define BNX2_RPM_RC_CNTL_13_HDR_TYPE_DATA_XI         (4L<<13)
3934 #define BNX2_RPM_RC_CNTL_13_HDR_TYPE_TCP_UDP_XI      (5L<<13)
3935 #define BNX2_RPM_RC_CNTL_13_HDR_TYPE_ICMPV6_XI       (6L<<13)
3936 #define BNX2_RPM_RC_CNTL_13_COMP_XI          (0x3L<<16)
3937 #define BNX2_RPM_RC_CNTL_13_COMP_EQUAL_XI        (0L<<16)
3938 #define BNX2_RPM_RC_CNTL_13_COMP_NEQUAL_XI       (1L<<16)
3939 #define BNX2_RPM_RC_CNTL_13_COMP_GREATER_XI      (2L<<16)
3940 #define BNX2_RPM_RC_CNTL_13_COMP_LESS_XI         (3L<<16)
3941 #define BNX2_RPM_RC_CNTL_13_MAP_XI           (1L<<18)
3942 #define BNX2_RPM_RC_CNTL_13_SBIT_XI          (1L<<19)
3943 #define BNX2_RPM_RC_CNTL_13_CMDSEL_XI            (0x1fL<<20)
3944 #define BNX2_RPM_RC_CNTL_13_DISCARD_XI           (1L<<25)
3945 #define BNX2_RPM_RC_CNTL_13_MASK_XI          (1L<<26)
3946 #define BNX2_RPM_RC_CNTL_13_P1_XI            (1L<<27)
3947 #define BNX2_RPM_RC_CNTL_13_P2_XI            (1L<<28)
3948 #define BNX2_RPM_RC_CNTL_13_P3_XI            (1L<<29)
3949 #define BNX2_RPM_RC_CNTL_13_NBIT_XI          (1L<<30)
3950 
3951 #define BNX2_RPM_RC_VALUE_MASK_13           0x0000196c
3952 #define BNX2_RPM_RC_VALUE_MASK_13_VALUE          (0xffffL<<0)
3953 #define BNX2_RPM_RC_VALUE_MASK_13_MASK           (0xffffL<<16)
3954 
3955 #define BNX2_RPM_RC_CNTL_14             0x00001970
3956 #define BNX2_RPM_RC_CNTL_14_A                (0x3ffffL<<0)
3957 #define BNX2_RPM_RC_CNTL_14_B                (0xfffL<<19)
3958 #define BNX2_RPM_RC_CNTL_14_OFFSET_XI            (0xffL<<0)
3959 #define BNX2_RPM_RC_CNTL_14_CLASS_XI             (0x7L<<8)
3960 #define BNX2_RPM_RC_CNTL_14_PRIORITY_XI          (1L<<11)
3961 #define BNX2_RPM_RC_CNTL_14_P4_XI            (1L<<12)
3962 #define BNX2_RPM_RC_CNTL_14_HDR_TYPE_XI          (0x7L<<13)
3963 #define BNX2_RPM_RC_CNTL_14_HDR_TYPE_START_XI        (0L<<13)
3964 #define BNX2_RPM_RC_CNTL_14_HDR_TYPE_IP_XI       (1L<<13)
3965 #define BNX2_RPM_RC_CNTL_14_HDR_TYPE_TCP_XI      (2L<<13)
3966 #define BNX2_RPM_RC_CNTL_14_HDR_TYPE_UDP_XI      (3L<<13)
3967 #define BNX2_RPM_RC_CNTL_14_HDR_TYPE_DATA_XI         (4L<<13)
3968 #define BNX2_RPM_RC_CNTL_14_HDR_TYPE_TCP_UDP_XI      (5L<<13)
3969 #define BNX2_RPM_RC_CNTL_14_HDR_TYPE_ICMPV6_XI       (6L<<13)
3970 #define BNX2_RPM_RC_CNTL_14_COMP_XI          (0x3L<<16)
3971 #define BNX2_RPM_RC_CNTL_14_COMP_EQUAL_XI        (0L<<16)
3972 #define BNX2_RPM_RC_CNTL_14_COMP_NEQUAL_XI       (1L<<16)
3973 #define BNX2_RPM_RC_CNTL_14_COMP_GREATER_XI      (2L<<16)
3974 #define BNX2_RPM_RC_CNTL_14_COMP_LESS_XI         (3L<<16)
3975 #define BNX2_RPM_RC_CNTL_14_MAP_XI           (1L<<18)
3976 #define BNX2_RPM_RC_CNTL_14_SBIT_XI          (1L<<19)
3977 #define BNX2_RPM_RC_CNTL_14_CMDSEL_XI            (0x1fL<<20)
3978 #define BNX2_RPM_RC_CNTL_14_DISCARD_XI           (1L<<25)
3979 #define BNX2_RPM_RC_CNTL_14_MASK_XI          (1L<<26)
3980 #define BNX2_RPM_RC_CNTL_14_P1_XI            (1L<<27)
3981 #define BNX2_RPM_RC_CNTL_14_P2_XI            (1L<<28)
3982 #define BNX2_RPM_RC_CNTL_14_P3_XI            (1L<<29)
3983 #define BNX2_RPM_RC_CNTL_14_NBIT_XI          (1L<<30)
3984 
3985 #define BNX2_RPM_RC_VALUE_MASK_14           0x00001974
3986 #define BNX2_RPM_RC_VALUE_MASK_14_VALUE          (0xffffL<<0)
3987 #define BNX2_RPM_RC_VALUE_MASK_14_MASK           (0xffffL<<16)
3988 
3989 #define BNX2_RPM_RC_CNTL_15             0x00001978
3990 #define BNX2_RPM_RC_CNTL_15_A                (0x3ffffL<<0)
3991 #define BNX2_RPM_RC_CNTL_15_B                (0xfffL<<19)
3992 #define BNX2_RPM_RC_CNTL_15_OFFSET_XI            (0xffL<<0)
3993 #define BNX2_RPM_RC_CNTL_15_CLASS_XI             (0x7L<<8)
3994 #define BNX2_RPM_RC_CNTL_15_PRIORITY_XI          (1L<<11)
3995 #define BNX2_RPM_RC_CNTL_15_P4_XI            (1L<<12)
3996 #define BNX2_RPM_RC_CNTL_15_HDR_TYPE_XI          (0x7L<<13)
3997 #define BNX2_RPM_RC_CNTL_15_HDR_TYPE_START_XI        (0L<<13)
3998 #define BNX2_RPM_RC_CNTL_15_HDR_TYPE_IP_XI       (1L<<13)
3999 #define BNX2_RPM_RC_CNTL_15_HDR_TYPE_TCP_XI      (2L<<13)
4000 #define BNX2_RPM_RC_CNTL_15_HDR_TYPE_UDP_XI      (3L<<13)
4001 #define BNX2_RPM_RC_CNTL_15_HDR_TYPE_DATA_XI         (4L<<13)
4002 #define BNX2_RPM_RC_CNTL_15_HDR_TYPE_TCP_UDP_XI      (5L<<13)
4003 #define BNX2_RPM_RC_CNTL_15_HDR_TYPE_ICMPV6_XI       (6L<<13)
4004 #define BNX2_RPM_RC_CNTL_15_COMP_XI          (0x3L<<16)
4005 #define BNX2_RPM_RC_CNTL_15_COMP_EQUAL_XI        (0L<<16)
4006 #define BNX2_RPM_RC_CNTL_15_COMP_NEQUAL_XI       (1L<<16)
4007 #define BNX2_RPM_RC_CNTL_15_COMP_GREATER_XI      (2L<<16)
4008 #define BNX2_RPM_RC_CNTL_15_COMP_LESS_XI         (3L<<16)
4009 #define BNX2_RPM_RC_CNTL_15_MAP_XI           (1L<<18)
4010 #define BNX2_RPM_RC_CNTL_15_SBIT_XI          (1L<<19)
4011 #define BNX2_RPM_RC_CNTL_15_CMDSEL_XI            (0x1fL<<20)
4012 #define BNX2_RPM_RC_CNTL_15_DISCARD_XI           (1L<<25)
4013 #define BNX2_RPM_RC_CNTL_15_MASK_XI          (1L<<26)
4014 #define BNX2_RPM_RC_CNTL_15_P1_XI            (1L<<27)
4015 #define BNX2_RPM_RC_CNTL_15_P2_XI            (1L<<28)
4016 #define BNX2_RPM_RC_CNTL_15_P3_XI            (1L<<29)
4017 #define BNX2_RPM_RC_CNTL_15_NBIT_XI          (1L<<30)
4018 
4019 #define BNX2_RPM_RC_VALUE_MASK_15           0x0000197c
4020 #define BNX2_RPM_RC_VALUE_MASK_15_VALUE          (0xffffL<<0)
4021 #define BNX2_RPM_RC_VALUE_MASK_15_MASK           (0xffffL<<16)
4022 
4023 #define BNX2_RPM_RC_CONFIG              0x00001980
4024 #define BNX2_RPM_RC_CONFIG_RULE_ENABLE           (0xffffL<<0)
4025 #define BNX2_RPM_RC_CONFIG_RULE_ENABLE_XI        (0xfffffL<<0)
4026 #define BNX2_RPM_RC_CONFIG_DEF_CLASS             (0x7L<<24)
4027 #define BNX2_RPM_RC_CONFIG_KNUM_OVERWRITE        (1L<<31)
4028 
4029 #define BNX2_RPM_DEBUG0                 0x00001984
4030 #define BNX2_RPM_DEBUG0_FM_BCNT              (0xffffL<<0)
4031 #define BNX2_RPM_DEBUG0_T_DATA_OFST_VLD          (1L<<16)
4032 #define BNX2_RPM_DEBUG0_T_UDP_OFST_VLD           (1L<<17)
4033 #define BNX2_RPM_DEBUG0_T_TCP_OFST_VLD           (1L<<18)
4034 #define BNX2_RPM_DEBUG0_T_IP_OFST_VLD            (1L<<19)
4035 #define BNX2_RPM_DEBUG0_IP_MORE_FRGMT            (1L<<20)
4036 #define BNX2_RPM_DEBUG0_T_IP_NO_TCP_UDP_HDR      (1L<<21)
4037 #define BNX2_RPM_DEBUG0_LLC_SNAP             (1L<<22)
4038 #define BNX2_RPM_DEBUG0_FM_STARTED           (1L<<23)
4039 #define BNX2_RPM_DEBUG0_DONE                 (1L<<24)
4040 #define BNX2_RPM_DEBUG0_WAIT_4_DONE          (1L<<25)
4041 #define BNX2_RPM_DEBUG0_USE_TPBUF_CKSUM          (1L<<26)
4042 #define BNX2_RPM_DEBUG0_RX_NO_PSD_HDR_CKSUM      (1L<<27)
4043 #define BNX2_RPM_DEBUG0_IGNORE_VLAN          (1L<<28)
4044 #define BNX2_RPM_DEBUG0_RP_ENA_ACTIVE            (1L<<31)
4045 
4046 #define BNX2_RPM_DEBUG1                 0x00001988
4047 #define BNX2_RPM_DEBUG1_FSM_CUR_ST           (0xffffL<<0)
4048 #define BNX2_RPM_DEBUG1_FSM_CUR_ST_IDLE          (0L<<0)
4049 #define BNX2_RPM_DEBUG1_FSM_CUR_ST_ETYPE_B6_ALL      (1L<<0)
4050 #define BNX2_RPM_DEBUG1_FSM_CUR_ST_ETYPE_B2_IPLLC    (2L<<0)
4051 #define BNX2_RPM_DEBUG1_FSM_CUR_ST_ETYPE_B6_IP       (4L<<0)
4052 #define BNX2_RPM_DEBUG1_FSM_CUR_ST_ETYPE_B2_IP       (8L<<0)
4053 #define BNX2_RPM_DEBUG1_FSM_CUR_ST_IP_START      (16L<<0)
4054 #define BNX2_RPM_DEBUG1_FSM_CUR_ST_IP            (32L<<0)
4055 #define BNX2_RPM_DEBUG1_FSM_CUR_ST_TCP           (64L<<0)
4056 #define BNX2_RPM_DEBUG1_FSM_CUR_ST_UDP           (128L<<0)
4057 #define BNX2_RPM_DEBUG1_FSM_CUR_ST_AH            (256L<<0)
4058 #define BNX2_RPM_DEBUG1_FSM_CUR_ST_ESP           (512L<<0)
4059 #define BNX2_RPM_DEBUG1_FSM_CUR_ST_ESP_PAYLOAD       (1024L<<0)
4060 #define BNX2_RPM_DEBUG1_FSM_CUR_ST_DATA          (2048L<<0)
4061 #define BNX2_RPM_DEBUG1_FSM_CUR_ST_ADD_CARRY         (0x2000L<<0)
4062 #define BNX2_RPM_DEBUG1_FSM_CUR_ST_ADD_CARRYOUT      (0x4000L<<0)
4063 #define BNX2_RPM_DEBUG1_FSM_CUR_ST_LATCH_RESULT      (0x8000L<<0)
4064 #define BNX2_RPM_DEBUG1_HDR_BCNT             (0x7ffL<<16)
4065 #define BNX2_RPM_DEBUG1_UNKNOWN_ETYPE_D          (1L<<28)
4066 #define BNX2_RPM_DEBUG1_VLAN_REMOVED_D2          (1L<<29)
4067 #define BNX2_RPM_DEBUG1_VLAN_REMOVED_D1          (1L<<30)
4068 #define BNX2_RPM_DEBUG1_EOF_0XTRA_WD             (1L<<31)
4069 
4070 #define BNX2_RPM_DEBUG2                 0x0000198c
4071 #define BNX2_RPM_DEBUG2_CMD_HIT_VEC          (0xffffL<<0)
4072 #define BNX2_RPM_DEBUG2_IP_BCNT              (0xffL<<16)
4073 #define BNX2_RPM_DEBUG2_THIS_CMD_M4          (1L<<24)
4074 #define BNX2_RPM_DEBUG2_THIS_CMD_M3          (1L<<25)
4075 #define BNX2_RPM_DEBUG2_THIS_CMD_M2          (1L<<26)
4076 #define BNX2_RPM_DEBUG2_THIS_CMD_M1          (1L<<27)
4077 #define BNX2_RPM_DEBUG2_IPIPE_EMPTY          (1L<<28)
4078 #define BNX2_RPM_DEBUG2_FM_DISCARD           (1L<<29)
4079 #define BNX2_RPM_DEBUG2_LAST_RULE_IN_FM_D2       (1L<<30)
4080 #define BNX2_RPM_DEBUG2_LAST_RULE_IN_FM_D1       (1L<<31)
4081 
4082 #define BNX2_RPM_DEBUG3                 0x00001990
4083 #define BNX2_RPM_DEBUG3_AVAIL_MBUF_PTR           (0x1ffL<<0)
4084 #define BNX2_RPM_DEBUG3_RDE_RLUPQ_WR_REQ_INT         (1L<<9)
4085 #define BNX2_RPM_DEBUG3_RDE_RBUF_WR_LAST_INT         (1L<<10)
4086 #define BNX2_RPM_DEBUG3_RDE_RBUF_WR_REQ_INT      (1L<<11)
4087 #define BNX2_RPM_DEBUG3_RDE_RBUF_FREE_REQ        (1L<<12)
4088 #define BNX2_RPM_DEBUG3_RDE_RBUF_ALLOC_REQ       (1L<<13)
4089 #define BNX2_RPM_DEBUG3_DFSM_MBUF_NOTAVAIL       (1L<<14)
4090 #define BNX2_RPM_DEBUG3_RBUF_RDE_SOF_DROP        (1L<<15)
4091 #define BNX2_RPM_DEBUG3_DFIFO_VLD_ENTRY_CT       (0xfL<<16)
4092 #define BNX2_RPM_DEBUG3_RDE_SRC_FIFO_ALMFULL         (1L<<21)
4093 #define BNX2_RPM_DEBUG3_DROP_NXT_VLD             (1L<<22)
4094 #define BNX2_RPM_DEBUG3_DROP_NXT             (1L<<23)
4095 #define BNX2_RPM_DEBUG3_FTQ_FSM              (0x3L<<24)
4096 #define BNX2_RPM_DEBUG3_FTQ_FSM_IDLE             (0x0L<<24)
4097 #define BNX2_RPM_DEBUG3_FTQ_FSM_WAIT_ACK         (0x1L<<24)
4098 #define BNX2_RPM_DEBUG3_FTQ_FSM_WAIT_FREE        (0x2L<<24)
4099 #define BNX2_RPM_DEBUG3_MBWRITE_FSM          (0x3L<<26)
4100 #define BNX2_RPM_DEBUG3_MBWRITE_FSM_WAIT_SOF         (0x0L<<26)
4101 #define BNX2_RPM_DEBUG3_MBWRITE_FSM_GET_MBUF         (0x1L<<26)
4102 #define BNX2_RPM_DEBUG3_MBWRITE_FSM_DMA_DATA         (0x2L<<26)
4103 #define BNX2_RPM_DEBUG3_MBWRITE_FSM_WAIT_DATA        (0x3L<<26)
4104 #define BNX2_RPM_DEBUG3_MBWRITE_FSM_WAIT_EOF         (0x4L<<26)
4105 #define BNX2_RPM_DEBUG3_MBWRITE_FSM_WAIT_MF_ACK      (0x5L<<26)
4106 #define BNX2_RPM_DEBUG3_MBWRITE_FSM_WAIT_DROP_NXT_VLD    (0x6L<<26)
4107 #define BNX2_RPM_DEBUG3_MBWRITE_FSM_DONE         (0x7L<<26)
4108 #define BNX2_RPM_DEBUG3_MBFREE_FSM           (1L<<29)
4109 #define BNX2_RPM_DEBUG3_MBFREE_FSM_IDLE          (0L<<29)
4110 #define BNX2_RPM_DEBUG3_MBFREE_FSM_WAIT_ACK      (1L<<29)
4111 #define BNX2_RPM_DEBUG3_MBALLOC_FSM          (1L<<30)
4112 #define BNX2_RPM_DEBUG3_MBALLOC_FSM_ET_MBUF      (0x0L<<30)
4113 #define BNX2_RPM_DEBUG3_MBALLOC_FSM_IVE_MBUF         (0x1L<<30)
4114 #define BNX2_RPM_DEBUG3_CCODE_EOF_ERROR          (1L<<31)
4115 
4116 #define BNX2_RPM_DEBUG4                 0x00001994
4117 #define BNX2_RPM_DEBUG4_DFSM_MBUF_CLUSTER        (0x1ffffffL<<0)
4118 #define BNX2_RPM_DEBUG4_DFIFO_CUR_CCODE          (0x7L<<25)
4119 #define BNX2_RPM_DEBUG4_MBWRITE_FSM          (0x7L<<28)
4120 #define BNX2_RPM_DEBUG4_DFIFO_EMPTY          (1L<<31)
4121 
4122 #define BNX2_RPM_DEBUG5                 0x00001998
4123 #define BNX2_RPM_DEBUG5_RDROP_WPTR           (0x1fL<<0)
4124 #define BNX2_RPM_DEBUG5_RDROP_ACPI_RPTR          (0x1fL<<5)
4125 #define BNX2_RPM_DEBUG5_RDROP_MC_RPTR            (0x1fL<<10)
4126 #define BNX2_RPM_DEBUG5_RDROP_RC_RPTR            (0x1fL<<15)
4127 #define BNX2_RPM_DEBUG5_RDROP_ACPI_EMPTY         (1L<<20)
4128 #define BNX2_RPM_DEBUG5_RDROP_MC_EMPTY           (1L<<21)
4129 #define BNX2_RPM_DEBUG5_RDROP_AEOF_VEC_AT_RDROP_MC_RPTR  (1L<<22)
4130 #define BNX2_RPM_DEBUG5_HOLDREG_WOL_DROP_INT         (1L<<23)
4131 #define BNX2_RPM_DEBUG5_HOLDREG_DISCARD          (1L<<24)
4132 #define BNX2_RPM_DEBUG5_HOLDREG_MBUF_NOTAVAIL        (1L<<25)
4133 #define BNX2_RPM_DEBUG5_HOLDREG_MC_EMPTY         (1L<<26)
4134 #define BNX2_RPM_DEBUG5_HOLDREG_RC_EMPTY         (1L<<27)
4135 #define BNX2_RPM_DEBUG5_HOLDREG_FC_EMPTY         (1L<<28)
4136 #define BNX2_RPM_DEBUG5_HOLDREG_ACPI_EMPTY       (1L<<29)
4137 #define BNX2_RPM_DEBUG5_HOLDREG_FULL_T           (1L<<30)
4138 #define BNX2_RPM_DEBUG5_HOLDREG_RD           (1L<<31)
4139 
4140 #define BNX2_RPM_DEBUG6                 0x0000199c
4141 #define BNX2_RPM_DEBUG6_ACPI_VEC             (0xffffL<<0)
4142 #define BNX2_RPM_DEBUG6_VEC              (0xffffL<<16)
4143 
4144 #define BNX2_RPM_DEBUG7                 0x000019a0
4145 #define BNX2_RPM_DEBUG7_RPM_DBG7_LAST_CRC        (0xffffffffL<<0)
4146 
4147 #define BNX2_RPM_DEBUG8                 0x000019a4
4148 #define BNX2_RPM_DEBUG8_PS_ACPI_FSM          (0xfL<<0)
4149 #define BNX2_RPM_DEBUG8_PS_ACPI_FSM_IDLE         (0L<<0)
4150 #define BNX2_RPM_DEBUG8_PS_ACPI_FSM_SOF_W1_ADDR      (1L<<0)
4151 #define BNX2_RPM_DEBUG8_PS_ACPI_FSM_SOF_W2_ADDR      (2L<<0)
4152 #define BNX2_RPM_DEBUG8_PS_ACPI_FSM_SOF_W3_ADDR      (3L<<0)
4153 #define BNX2_RPM_DEBUG8_PS_ACPI_FSM_SOF_WAIT_THBUF   (4L<<0)
4154 #define BNX2_RPM_DEBUG8_PS_ACPI_FSM_W3_DATA      (5L<<0)
4155 #define BNX2_RPM_DEBUG8_PS_ACPI_FSM_W0_ADDR      (6L<<0)
4156 #define BNX2_RPM_DEBUG8_PS_ACPI_FSM_W1_ADDR      (7L<<0)
4157 #define BNX2_RPM_DEBUG8_PS_ACPI_FSM_W2_ADDR      (8L<<0)
4158 #define BNX2_RPM_DEBUG8_PS_ACPI_FSM_W3_ADDR      (9L<<0)
4159 #define BNX2_RPM_DEBUG8_PS_ACPI_FSM_WAIT_THBUF       (10L<<0)
4160 #define BNX2_RPM_DEBUG8_COMPARE_AT_W0            (1L<<4)
4161 #define BNX2_RPM_DEBUG8_COMPARE_AT_W3_DATA       (1L<<5)
4162 #define BNX2_RPM_DEBUG8_COMPARE_AT_SOF_WAIT      (1L<<6)
4163 #define BNX2_RPM_DEBUG8_COMPARE_AT_SOF_W3        (1L<<7)
4164 #define BNX2_RPM_DEBUG8_COMPARE_AT_SOF_W2        (1L<<8)
4165 #define BNX2_RPM_DEBUG8_EOF_W_LTEQ6_VLDBYTES         (1L<<9)
4166 #define BNX2_RPM_DEBUG8_EOF_W_LTEQ4_VLDBYTES         (1L<<10)
4167 #define BNX2_RPM_DEBUG8_NXT_EOF_W_12_VLDBYTES        (1L<<11)
4168 #define BNX2_RPM_DEBUG8_EOF_DET              (1L<<12)
4169 #define BNX2_RPM_DEBUG8_SOF_DET              (1L<<13)
4170 #define BNX2_RPM_DEBUG8_WAIT_4_SOF           (1L<<14)
4171 #define BNX2_RPM_DEBUG8_ALL_DONE             (1L<<15)
4172 #define BNX2_RPM_DEBUG8_THBUF_ADDR           (0x7fL<<16)
4173 #define BNX2_RPM_DEBUG8_BYTE_CTR             (0xffL<<24)
4174 
4175 #define BNX2_RPM_DEBUG9                 0x000019a8
4176 #define BNX2_RPM_DEBUG9_OUTFIFO_COUNT            (0x7L<<0)
4177 #define BNX2_RPM_DEBUG9_RDE_ACPI_RDY             (1L<<3)
4178 #define BNX2_RPM_DEBUG9_VLD_RD_ENTRY_CT          (0x7L<<4)
4179 #define BNX2_RPM_DEBUG9_OUTFIFO_OVERRUN_OCCURRED     (1L<<28)
4180 #define BNX2_RPM_DEBUG9_INFIFO_OVERRUN_OCCURRED      (1L<<29)
4181 #define BNX2_RPM_DEBUG9_ACPI_MATCH_INT           (1L<<30)
4182 #define BNX2_RPM_DEBUG9_ACPI_ENABLE_SYN          (1L<<31)
4183 #define BNX2_RPM_DEBUG9_BEMEM_R_XI           (0x1fL<<0)
4184 #define BNX2_RPM_DEBUG9_EO_XI                (1L<<5)
4185 #define BNX2_RPM_DEBUG9_AEOF_DE_XI           (1L<<6)
4186 #define BNX2_RPM_DEBUG9_SO_XI                (1L<<7)
4187 #define BNX2_RPM_DEBUG9_WD64_CT_XI           (0x1fL<<8)
4188 #define BNX2_RPM_DEBUG9_EOF_VLDBYTE_XI           (0x7L<<13)
4189 #define BNX2_RPM_DEBUG9_ACPI_RDE_PAT_ID_XI       (0xfL<<16)
4190 #define BNX2_RPM_DEBUG9_CALCRC_RESULT_XI         (0x3ffL<<20)
4191 #define BNX2_RPM_DEBUG9_DATA_IN_VL_XI            (1L<<30)
4192 #define BNX2_RPM_DEBUG9_CALCRC_BUFFER_VLD_XI         (1L<<31)
4193 
4194 #define BNX2_RPM_ACPI_DBG_BUF_W00           0x000019c0
4195 #define BNX2_RPM_ACPI_DBG_BUF_W01           0x000019c4
4196 #define BNX2_RPM_ACPI_DBG_BUF_W02           0x000019c8
4197 #define BNX2_RPM_ACPI_DBG_BUF_W03           0x000019cc
4198 #define BNX2_RPM_ACPI_DBG_BUF_W10           0x000019d0
4199 #define BNX2_RPM_ACPI_DBG_BUF_W11           0x000019d4
4200 #define BNX2_RPM_ACPI_DBG_BUF_W12           0x000019d8
4201 #define BNX2_RPM_ACPI_DBG_BUF_W13           0x000019dc
4202 #define BNX2_RPM_ACPI_DBG_BUF_W20           0x000019e0
4203 #define BNX2_RPM_ACPI_DBG_BUF_W21           0x000019e4
4204 #define BNX2_RPM_ACPI_DBG_BUF_W22           0x000019e8
4205 #define BNX2_RPM_ACPI_DBG_BUF_W23           0x000019ec
4206 #define BNX2_RPM_ACPI_DBG_BUF_W30           0x000019f0
4207 #define BNX2_RPM_ACPI_DBG_BUF_W31           0x000019f4
4208 #define BNX2_RPM_ACPI_DBG_BUF_W32           0x000019f8
4209 #define BNX2_RPM_ACPI_DBG_BUF_W33           0x000019fc
4210 #define BNX2_RPM_ACPI_BYTE_ENABLE_CTRL          0x00001a00
4211 #define BNX2_RPM_ACPI_BYTE_ENABLE_CTRL_BYTE_ADDRESS  (0xffffL<<0)
4212 #define BNX2_RPM_ACPI_BYTE_ENABLE_CTRL_DEBUGRD       (1L<<28)
4213 #define BNX2_RPM_ACPI_BYTE_ENABLE_CTRL_MODE      (1L<<29)
4214 #define BNX2_RPM_ACPI_BYTE_ENABLE_CTRL_INIT      (1L<<30)
4215 #define BNX2_RPM_ACPI_BYTE_ENABLE_CTRL_WR        (1L<<31)
4216 
4217 #define BNX2_RPM_ACPI_PATTERN_CTRL          0x00001a04
4218 #define BNX2_RPM_ACPI_PATTERN_CTRL_PATTERN_ID        (0xfL<<0)
4219 #define BNX2_RPM_ACPI_PATTERN_CTRL_CRC_SM_CLR        (1L<<30)
4220 #define BNX2_RPM_ACPI_PATTERN_CTRL_WR            (1L<<31)
4221 
4222 #define BNX2_RPM_ACPI_DATA              0x00001a08
4223 #define BNX2_RPM_ACPI_DATA_PATTERN_BE            (0xffffffffL<<0)
4224 
4225 #define BNX2_RPM_ACPI_PATTERN_LEN0          0x00001a0c
4226 #define BNX2_RPM_ACPI_PATTERN_LEN0_PATTERN_LEN3      (0xffL<<0)
4227 #define BNX2_RPM_ACPI_PATTERN_LEN0_PATTERN_LEN2      (0xffL<<8)
4228 #define BNX2_RPM_ACPI_PATTERN_LEN0_PATTERN_LEN1      (0xffL<<16)
4229 #define BNX2_RPM_ACPI_PATTERN_LEN0_PATTERN_LEN0      (0xffL<<24)
4230 
4231 #define BNX2_RPM_ACPI_PATTERN_LEN1          0x00001a10
4232 #define BNX2_RPM_ACPI_PATTERN_LEN1_PATTERN_LEN7      (0xffL<<0)
4233 #define BNX2_RPM_ACPI_PATTERN_LEN1_PATTERN_LEN6      (0xffL<<8)
4234 #define BNX2_RPM_ACPI_PATTERN_LEN1_PATTERN_LEN5      (0xffL<<16)
4235 #define BNX2_RPM_ACPI_PATTERN_LEN1_PATTERN_LEN4      (0xffL<<24)
4236 
4237 #define BNX2_RPM_ACPI_PATTERN_CRC0          0x00001a18
4238 #define BNX2_RPM_ACPI_PATTERN_CRC0_PATTERN_CRC0      (0xffffffffL<<0)
4239 
4240 #define BNX2_RPM_ACPI_PATTERN_CRC1          0x00001a1c
4241 #define BNX2_RPM_ACPI_PATTERN_CRC1_PATTERN_CRC1      (0xffffffffL<<0)
4242 
4243 #define BNX2_RPM_ACPI_PATTERN_CRC2          0x00001a20
4244 #define BNX2_RPM_ACPI_PATTERN_CRC2_PATTERN_CRC2      (0xffffffffL<<0)
4245 
4246 #define BNX2_RPM_ACPI_PATTERN_CRC3          0x00001a24
4247 #define BNX2_RPM_ACPI_PATTERN_CRC3_PATTERN_CRC3      (0xffffffffL<<0)
4248 
4249 #define BNX2_RPM_ACPI_PATTERN_CRC4          0x00001a28
4250 #define BNX2_RPM_ACPI_PATTERN_CRC4_PATTERN_CRC4      (0xffffffffL<<0)
4251 
4252 #define BNX2_RPM_ACPI_PATTERN_CRC5          0x00001a2c
4253 #define BNX2_RPM_ACPI_PATTERN_CRC5_PATTERN_CRC5      (0xffffffffL<<0)
4254 
4255 #define BNX2_RPM_ACPI_PATTERN_CRC6          0x00001a30
4256 #define BNX2_RPM_ACPI_PATTERN_CRC6_PATTERN_CRC6      (0xffffffffL<<0)
4257 
4258 #define BNX2_RPM_ACPI_PATTERN_CRC7          0x00001a34
4259 #define BNX2_RPM_ACPI_PATTERN_CRC7_PATTERN_CRC7      (0xffffffffL<<0)
4260 
4261 
4262 /*
4263  *  rlup_reg definition
4264  *  offset: 0x2000
4265  */
4266 #define BNX2_RLUP_RSS_CONFIG                0x0000201c
4267 #define BNX2_RLUP_RSS_CONFIG_IPV4_RSS_TYPE_XI        (0x3L<<0)
4268 #define BNX2_RLUP_RSS_CONFIG_IPV4_RSS_TYPE_OFF_XI    (0L<<0)
4269 #define BNX2_RLUP_RSS_CONFIG_IPV4_RSS_TYPE_ALL_XI    (1L<<0)
4270 #define BNX2_RLUP_RSS_CONFIG_IPV4_RSS_TYPE_IP_ONLY_XI    (2L<<0)
4271 #define BNX2_RLUP_RSS_CONFIG_IPV4_RSS_TYPE_RES_XI    (3L<<0)
4272 #define BNX2_RLUP_RSS_CONFIG_IPV6_RSS_TYPE_XI        (0x3L<<2)
4273 #define BNX2_RLUP_RSS_CONFIG_IPV6_RSS_TYPE_OFF_XI    (0L<<2)
4274 #define BNX2_RLUP_RSS_CONFIG_IPV6_RSS_TYPE_ALL_XI    (1L<<2)
4275 #define BNX2_RLUP_RSS_CONFIG_IPV6_RSS_TYPE_IP_ONLY_XI    (2L<<2)
4276 #define BNX2_RLUP_RSS_CONFIG_IPV6_RSS_TYPE_RES_XI    (3L<<2)
4277 
4278 
4279 /*
4280  *  rbuf_reg definition
4281  *  offset: 0x200000
4282  */
4283 #define BNX2_RBUF_COMMAND               0x00200000
4284 #define BNX2_RBUF_COMMAND_ENABLED            (1L<<0)
4285 #define BNX2_RBUF_COMMAND_FREE_INIT          (1L<<1)
4286 #define BNX2_RBUF_COMMAND_RAM_INIT           (1L<<2)
4287 #define BNX2_RBUF_COMMAND_PKT_OFFSET_OVFL        (1L<<3)
4288 #define BNX2_RBUF_COMMAND_OVER_FREE          (1L<<4)
4289 #define BNX2_RBUF_COMMAND_ALLOC_REQ          (1L<<5)
4290 #define BNX2_RBUF_COMMAND_EN_PRI_CHNGE_TE        (1L<<6)
4291 #define BNX2_RBUF_COMMAND_CU_ISOLATE_XI          (1L<<5)
4292 #define BNX2_RBUF_COMMAND_EN_PRI_CHANGE_XI       (1L<<6)
4293 #define BNX2_RBUF_COMMAND_GRC_ENDIAN_CONV_DIS_XI     (1L<<7)
4294 
4295 #define BNX2_RBUF_STATUS1               0x00200004
4296 #define BNX2_RBUF_STATUS1_FREE_COUNT             (0x3ffL<<0)
4297 
4298 #define BNX2_RBUF_STATUS2               0x00200008
4299 #define BNX2_RBUF_STATUS2_FREE_TAIL          (0x1ffL<<0)
4300 #define BNX2_RBUF_STATUS2_FREE_HEAD          (0x1ffL<<16)
4301 
4302 #define BNX2_RBUF_CONFIG                0x0020000c
4303 #define BNX2_RBUF_CONFIG_XOFF_TRIP           (0x3ffL<<0)
4304 #define BNX2_RBUF_CONFIG_XOFF_TRIP_VAL(mtu)      \
4305         ((((mtu) - 1500) * 31 / 1000) + 54)
4306 #define BNX2_RBUF_CONFIG_XON_TRIP            (0x3ffL<<16)
4307 #define BNX2_RBUF_CONFIG_XON_TRIP_VAL(mtu)       \
4308         ((((mtu) - 1500) * 39 / 1000) + 66)
4309 #define BNX2_RBUF_CONFIG_VAL(mtu)            \
4310         (BNX2_RBUF_CONFIG_XOFF_TRIP_VAL(mtu) |       \
4311         (BNX2_RBUF_CONFIG_XON_TRIP_VAL(mtu) << 16))
4312 
4313 #define BNX2_RBUF_FW_BUF_ALLOC              0x00200010
4314 #define BNX2_RBUF_FW_BUF_ALLOC_VALUE             (0x1ffL<<7)
4315 #define BNX2_RBUF_FW_BUF_ALLOC_TYPE          (1L<<16)
4316 #define BNX2_RBUF_FW_BUF_ALLOC_ALLOC_REQ         (1L<<31)
4317 
4318 #define BNX2_RBUF_FW_BUF_FREE               0x00200014
4319 #define BNX2_RBUF_FW_BUF_FREE_COUNT          (0x7fL<<0)
4320 #define BNX2_RBUF_FW_BUF_FREE_TAIL           (0x1ffL<<7)
4321 #define BNX2_RBUF_FW_BUF_FREE_HEAD           (0x1ffL<<16)
4322 #define BNX2_RBUF_FW_BUF_FREE_TYPE           (1L<<25)
4323 #define BNX2_RBUF_FW_BUF_FREE_FREE_REQ           (1L<<31)
4324 
4325 #define BNX2_RBUF_FW_BUF_SEL                0x00200018
4326 #define BNX2_RBUF_FW_BUF_SEL_COUNT           (0x7fL<<0)
4327 #define BNX2_RBUF_FW_BUF_SEL_TAIL            (0x1ffL<<7)
4328 #define BNX2_RBUF_FW_BUF_SEL_HEAD            (0x1ffL<<16)
4329 #define BNX2_RBUF_FW_BUF_SEL_SEL_REQ             (1L<<31)
4330 
4331 #define BNX2_RBUF_CONFIG2               0x0020001c
4332 #define BNX2_RBUF_CONFIG2_MAC_DROP_TRIP          (0x3ffL<<0)
4333 #define BNX2_RBUF_CONFIG2_MAC_DROP_TRIP_VAL(mtu)     \
4334         ((((mtu) - 1500) * 4 / 1000) + 5)
4335 #define BNX2_RBUF_CONFIG2_MAC_KEEP_TRIP          (0x3ffL<<16)
4336 #define BNX2_RBUF_CONFIG2_MAC_KEEP_TRIP_VAL(mtu)     \
4337         ((((mtu) - 1500) * 2 / 100) + 30)
4338 #define BNX2_RBUF_CONFIG2_VAL(mtu)           \
4339         (BNX2_RBUF_CONFIG2_MAC_DROP_TRIP_VAL(mtu) |  \
4340         (BNX2_RBUF_CONFIG2_MAC_KEEP_TRIP_VAL(mtu) << 16))
4341 
4342 #define BNX2_RBUF_CONFIG3               0x00200020
4343 #define BNX2_RBUF_CONFIG3_CU_DROP_TRIP           (0x3ffL<<0)
4344 #define BNX2_RBUF_CONFIG3_CU_DROP_TRIP_VAL(mtu)      \
4345         ((((mtu) - 1500) * 12 / 1000) + 18)
4346 #define BNX2_RBUF_CONFIG3_CU_KEEP_TRIP           (0x3ffL<<16)
4347 #define BNX2_RBUF_CONFIG3_CU_KEEP_TRIP_VAL(mtu)      \
4348         ((((mtu) - 1500) * 2 / 100) + 30)
4349 #define BNX2_RBUF_CONFIG3_VAL(mtu)           \
4350         (BNX2_RBUF_CONFIG3_CU_DROP_TRIP_VAL(mtu) |   \
4351         (BNX2_RBUF_CONFIG3_CU_KEEP_TRIP_VAL(mtu) << 16))
4352 
4353 #define BNX2_RBUF_PKT_DATA              0x00208000
4354 #define BNX2_RBUF_CLIST_DATA                0x00210000
4355 #define BNX2_RBUF_BUF_DATA              0x00220000
4356 
4357 
4358 /*
4359  *  rv2p_reg definition
4360  *  offset: 0x2800
4361  */
4362 #define BNX2_RV2P_COMMAND               0x00002800
4363 #define BNX2_RV2P_COMMAND_ENABLED            (1L<<0)
4364 #define BNX2_RV2P_COMMAND_PROC1_INTRPT           (1L<<1)
4365 #define BNX2_RV2P_COMMAND_PROC2_INTRPT           (1L<<2)
4366 #define BNX2_RV2P_COMMAND_ABORT0             (1L<<4)
4367 #define BNX2_RV2P_COMMAND_ABORT1             (1L<<5)
4368 #define BNX2_RV2P_COMMAND_ABORT2             (1L<<6)
4369 #define BNX2_RV2P_COMMAND_ABORT3             (1L<<7)
4370 #define BNX2_RV2P_COMMAND_ABORT4             (1L<<8)
4371 #define BNX2_RV2P_COMMAND_ABORT5             (1L<<9)
4372 #define BNX2_RV2P_COMMAND_PROC1_RESET            (1L<<16)
4373 #define BNX2_RV2P_COMMAND_PROC2_RESET            (1L<<17)
4374 #define BNX2_RV2P_COMMAND_CTXIF_RESET            (1L<<18)
4375 
4376 #define BNX2_RV2P_STATUS                0x00002804
4377 #define BNX2_RV2P_STATUS_ALWAYS_0            (1L<<0)
4378 #define BNX2_RV2P_STATUS_RV2P_GEN_STAT0_CNT      (1L<<8)
4379 #define BNX2_RV2P_STATUS_RV2P_GEN_STAT1_CNT      (1L<<9)
4380 #define BNX2_RV2P_STATUS_RV2P_GEN_STAT2_CNT      (1L<<10)
4381 #define BNX2_RV2P_STATUS_RV2P_GEN_STAT3_CNT      (1L<<11)
4382 #define BNX2_RV2P_STATUS_RV2P_GEN_STAT4_CNT      (1L<<12)
4383 #define BNX2_RV2P_STATUS_RV2P_GEN_STAT5_CNT      (1L<<13)
4384 
4385 #define BNX2_RV2P_CONFIG                0x00002808
4386 #define BNX2_RV2P_CONFIG_STALL_PROC1             (1L<<0)
4387 #define BNX2_RV2P_CONFIG_STALL_PROC2             (1L<<1)
4388 #define BNX2_RV2P_CONFIG_PROC1_STALL_ON_ABORT0       (1L<<8)
4389 #define BNX2_RV2P_CONFIG_PROC1_STALL_ON_ABORT1       (1L<<9)
4390 #define BNX2_RV2P_CONFIG_PROC1_STALL_ON_ABORT2       (1L<<10)
4391 #define BNX2_RV2P_CONFIG_PROC1_STALL_ON_ABORT3       (1L<<11)
4392 #define BNX2_RV2P_CONFIG_PROC1_STALL_ON_ABORT4       (1L<<12)
4393 #define BNX2_RV2P_CONFIG_PROC1_STALL_ON_ABORT5       (1L<<13)
4394 #define BNX2_RV2P_CONFIG_PROC2_STALL_ON_ABORT0       (1L<<16)
4395 #define BNX2_RV2P_CONFIG_PROC2_STALL_ON_ABORT1       (1L<<17)
4396 #define BNX2_RV2P_CONFIG_PROC2_STALL_ON_ABORT2       (1L<<18)
4397 #define BNX2_RV2P_CONFIG_PROC2_STALL_ON_ABORT3       (1L<<19)
4398 #define BNX2_RV2P_CONFIG_PROC2_STALL_ON_ABORT4       (1L<<20)
4399 #define BNX2_RV2P_CONFIG_PROC2_STALL_ON_ABORT5       (1L<<21)
4400 #define BNX2_RV2P_CONFIG_PAGE_SIZE           (0xfL<<24)
4401 #define BNX2_RV2P_CONFIG_PAGE_SIZE_256           (0L<<24)
4402 #define BNX2_RV2P_CONFIG_PAGE_SIZE_512           (1L<<24)
4403 #define BNX2_RV2P_CONFIG_PAGE_SIZE_1K            (2L<<24)
4404 #define BNX2_RV2P_CONFIG_PAGE_SIZE_2K            (3L<<24)
4405 #define BNX2_RV2P_CONFIG_PAGE_SIZE_4K            (4L<<24)
4406 #define BNX2_RV2P_CONFIG_PAGE_SIZE_8K            (5L<<24)
4407 #define BNX2_RV2P_CONFIG_PAGE_SIZE_16K           (6L<<24)
4408 #define BNX2_RV2P_CONFIG_PAGE_SIZE_32K           (7L<<24)
4409 #define BNX2_RV2P_CONFIG_PAGE_SIZE_64K           (8L<<24)
4410 #define BNX2_RV2P_CONFIG_PAGE_SIZE_128K          (9L<<24)
4411 #define BNX2_RV2P_CONFIG_PAGE_SIZE_256K          (10L<<24)
4412 #define BNX2_RV2P_CONFIG_PAGE_SIZE_512K          (11L<<24)
4413 #define BNX2_RV2P_CONFIG_PAGE_SIZE_1M            (12L<<24)
4414 
4415 #define BNX2_RV2P_GEN_BFR_ADDR_0            0x00002810
4416 #define BNX2_RV2P_GEN_BFR_ADDR_0_VALUE           (0xffffL<<16)
4417 
4418 #define BNX2_RV2P_GEN_BFR_ADDR_1            0x00002814
4419 #define BNX2_RV2P_GEN_BFR_ADDR_1_VALUE           (0xffffL<<16)
4420 
4421 #define BNX2_RV2P_GEN_BFR_ADDR_2            0x00002818
4422 #define BNX2_RV2P_GEN_BFR_ADDR_2_VALUE           (0xffffL<<16)
4423 
4424 #define BNX2_RV2P_GEN_BFR_ADDR_3            0x0000281c
4425 #define BNX2_RV2P_GEN_BFR_ADDR_3_VALUE           (0xffffL<<16)
4426 
4427 #define BNX2_RV2P_INSTR_HIGH                0x00002830
4428 #define BNX2_RV2P_INSTR_HIGH_HIGH            (0x1fL<<0)
4429 
4430 #define BNX2_RV2P_INSTR_LOW             0x00002834
4431 #define BNX2_RV2P_INSTR_LOW_LOW              (0xffffffffL<<0)
4432 
4433 #define BNX2_RV2P_PROC1_ADDR_CMD            0x00002838
4434 #define BNX2_RV2P_PROC1_ADDR_CMD_ADD             (0x3ffL<<0)
4435 #define BNX2_RV2P_PROC1_ADDR_CMD_RDWR            (1L<<31)
4436 
4437 #define BNX2_RV2P_PROC2_ADDR_CMD            0x0000283c
4438 #define BNX2_RV2P_PROC2_ADDR_CMD_ADD             (0x3ffL<<0)
4439 #define BNX2_RV2P_PROC2_ADDR_CMD_RDWR            (1L<<31)
4440 
4441 #define BNX2_RV2P_PROC1_GRC_DEBUG           0x00002840
4442 #define BNX2_RV2P_PROC2_GRC_DEBUG           0x00002844
4443 #define BNX2_RV2P_GRC_PROC_DEBUG            0x00002848
4444 #define BNX2_RV2P_DEBUG_VECT_PEEK           0x0000284c
4445 #define BNX2_RV2P_DEBUG_VECT_PEEK_1_VALUE        (0x7ffL<<0)
4446 #define BNX2_RV2P_DEBUG_VECT_PEEK_1_PEEK_EN      (1L<<11)
4447 #define BNX2_RV2P_DEBUG_VECT_PEEK_1_SEL          (0xfL<<12)
4448 #define BNX2_RV2P_DEBUG_VECT_PEEK_2_VALUE        (0x7ffL<<16)
4449 #define BNX2_RV2P_DEBUG_VECT_PEEK_2_PEEK_EN      (1L<<27)
4450 #define BNX2_RV2P_DEBUG_VECT_PEEK_2_SEL          (0xfL<<28)
4451 
4452 #define BNX2_RV2P_MPFE_PFE_CTL              0x00002afc
4453 #define BNX2_RV2P_MPFE_PFE_CTL_INC_USAGE_CNT         (1L<<0)
4454 #define BNX2_RV2P_MPFE_PFE_CTL_PFE_SIZE          (0xfL<<4)
4455 #define BNX2_RV2P_MPFE_PFE_CTL_PFE_SIZE_0        (0L<<4)
4456 #define BNX2_RV2P_MPFE_PFE_CTL_PFE_SIZE_1        (1L<<4)
4457 #define BNX2_RV2P_MPFE_PFE_CTL_PFE_SIZE_2        (2L<<4)
4458 #define BNX2_RV2P_MPFE_PFE_CTL_PFE_SIZE_3        (3L<<4)
4459 #define BNX2_RV2P_MPFE_PFE_CTL_PFE_SIZE_4        (4L<<4)
4460 #define BNX2_RV2P_MPFE_PFE_CTL_PFE_SIZE_5        (5L<<4)
4461 #define BNX2_RV2P_MPFE_PFE_CTL_PFE_SIZE_6        (6L<<4)
4462 #define BNX2_RV2P_MPFE_PFE_CTL_PFE_SIZE_7        (7L<<4)
4463 #define BNX2_RV2P_MPFE_PFE_CTL_PFE_SIZE_8        (8L<<4)
4464 #define BNX2_RV2P_MPFE_PFE_CTL_PFE_SIZE_9        (9L<<4)
4465 #define BNX2_RV2P_MPFE_PFE_CTL_PFE_SIZE_10       (10L<<4)
4466 #define BNX2_RV2P_MPFE_PFE_CTL_PFE_SIZE_11       (11L<<4)
4467 #define BNX2_RV2P_MPFE_PFE_CTL_PFE_SIZE_12       (12L<<4)
4468 #define BNX2_RV2P_MPFE_PFE_CTL_PFE_SIZE_13       (13L<<4)
4469 #define BNX2_RV2P_MPFE_PFE_CTL_PFE_SIZE_14       (14L<<4)
4470 #define BNX2_RV2P_MPFE_PFE_CTL_PFE_SIZE_15       (15L<<4)
4471 #define BNX2_RV2P_MPFE_PFE_CTL_PFE_COUNT         (0xfL<<12)
4472 #define BNX2_RV2P_MPFE_PFE_CTL_OFFSET            (0x1ffL<<16)
4473 
4474 #define BNX2_RV2P_RV2PPQ                0x00002b40
4475 #define BNX2_RV2P_PFTQ_CMD              0x00002b78
4476 #define BNX2_RV2P_PFTQ_CMD_OFFSET            (0x3ffL<<0)
4477 #define BNX2_RV2P_PFTQ_CMD_WR_TOP            (1L<<10)
4478 #define BNX2_RV2P_PFTQ_CMD_WR_TOP_0          (0L<<10)
4479 #define BNX2_RV2P_PFTQ_CMD_WR_TOP_1          (1L<<10)
4480 #define BNX2_RV2P_PFTQ_CMD_SFT_RESET             (1L<<25)
4481 #define BNX2_RV2P_PFTQ_CMD_RD_DATA           (1L<<26)
4482 #define BNX2_RV2P_PFTQ_CMD_ADD_INTERVEN          (1L<<27)
4483 #define BNX2_RV2P_PFTQ_CMD_ADD_DATA          (1L<<28)
4484 #define BNX2_RV2P_PFTQ_CMD_INTERVENE_CLR         (1L<<29)
4485 #define BNX2_RV2P_PFTQ_CMD_POP               (1L<<30)
4486 #define BNX2_RV2P_PFTQ_CMD_BUSY              (1L<<31)
4487 
4488 #define BNX2_RV2P_PFTQ_CTL              0x00002b7c
4489 #define BNX2_RV2P_PFTQ_CTL_INTERVENE             (1L<<0)
4490 #define BNX2_RV2P_PFTQ_CTL_OVERFLOW          (1L<<1)
4491 #define BNX2_RV2P_PFTQ_CTL_FORCE_INTERVENE       (1L<<2)
4492 #define BNX2_RV2P_PFTQ_CTL_MAX_DEPTH             (0x3ffL<<12)
4493 #define BNX2_RV2P_PFTQ_CTL_CUR_DEPTH             (0x3ffL<<22)
4494 
4495 #define BNX2_RV2P_RV2PTQ                0x00002b80
4496 #define BNX2_RV2P_TFTQ_CMD              0x00002bb8
4497 #define BNX2_RV2P_TFTQ_CMD_OFFSET            (0x3ffL<<0)
4498 #define BNX2_RV2P_TFTQ_CMD_WR_TOP            (1L<<10)
4499 #define BNX2_RV2P_TFTQ_CMD_WR_TOP_0          (0L<<10)
4500 #define BNX2_RV2P_TFTQ_CMD_WR_TOP_1          (1L<<10)
4501 #define BNX2_RV2P_TFTQ_CMD_SFT_RESET             (1L<<25)
4502 #define BNX2_RV2P_TFTQ_CMD_RD_DATA           (1L<<26)
4503 #define BNX2_RV2P_TFTQ_CMD_ADD_INTERVEN          (1L<<27)
4504 #define BNX2_RV2P_TFTQ_CMD_ADD_DATA          (1L<<28)
4505 #define BNX2_RV2P_TFTQ_CMD_INTERVENE_CLR         (1L<<29)
4506 #define BNX2_RV2P_TFTQ_CMD_POP               (1L<<30)
4507 #define BNX2_RV2P_TFTQ_CMD_BUSY              (1L<<31)
4508 
4509 #define BNX2_RV2P_TFTQ_CTL              0x00002bbc
4510 #define BNX2_RV2P_TFTQ_CTL_INTERVENE             (1L<<0)
4511 #define BNX2_RV2P_TFTQ_CTL_OVERFLOW          (1L<<1)
4512 #define BNX2_RV2P_TFTQ_CTL_FORCE_INTERVENE       (1L<<2)
4513 #define BNX2_RV2P_TFTQ_CTL_MAX_DEPTH             (0x3ffL<<12)
4514 #define BNX2_RV2P_TFTQ_CTL_CUR_DEPTH             (0x3ffL<<22)
4515 
4516 #define BNX2_RV2P_RV2PMQ                0x00002bc0
4517 #define BNX2_RV2P_MFTQ_CMD              0x00002bf8
4518 #define BNX2_RV2P_MFTQ_CMD_OFFSET            (0x3ffL<<0)
4519 #define BNX2_RV2P_MFTQ_CMD_WR_TOP            (1L<<10)
4520 #define BNX2_RV2P_MFTQ_CMD_WR_TOP_0          (0L<<10)
4521 #define BNX2_RV2P_MFTQ_CMD_WR_TOP_1          (1L<<10)
4522 #define BNX2_RV2P_MFTQ_CMD_SFT_RESET             (1L<<25)
4523 #define BNX2_RV2P_MFTQ_CMD_RD_DATA           (1L<<26)
4524 #define BNX2_RV2P_MFTQ_CMD_ADD_INTERVEN          (1L<<27)
4525 #define BNX2_RV2P_MFTQ_CMD_ADD_DATA          (1L<<28)
4526 #define BNX2_RV2P_MFTQ_CMD_INTERVENE_CLR         (1L<<29)
4527 #define BNX2_RV2P_MFTQ_CMD_POP               (1L<<30)
4528 #define BNX2_RV2P_MFTQ_CMD_BUSY              (1L<<31)
4529 
4530 #define BNX2_RV2P_MFTQ_CTL              0x00002bfc
4531 #define BNX2_RV2P_MFTQ_CTL_INTERVENE             (1L<<0)
4532 #define BNX2_RV2P_MFTQ_CTL_OVERFLOW          (1L<<1)
4533 #define BNX2_RV2P_MFTQ_CTL_FORCE_INTERVENE       (1L<<2)
4534 #define BNX2_RV2P_MFTQ_CTL_MAX_DEPTH             (0x3ffL<<12)
4535 #define BNX2_RV2P_MFTQ_CTL_CUR_DEPTH             (0x3ffL<<22)
4536 
4537 
4538 
4539 /*
4540  *  mq_reg definition
4541  *  offset: 0x3c00
4542  */
4543 #define BNX2_MQ_COMMAND                 0x00003c00
4544 #define BNX2_MQ_COMMAND_ENABLED              (1L<<0)
4545 #define BNX2_MQ_COMMAND_INIT                 (1L<<1)
4546 #define BNX2_MQ_COMMAND_OVERFLOW             (1L<<4)
4547 #define BNX2_MQ_COMMAND_WR_ERROR             (1L<<5)
4548 #define BNX2_MQ_COMMAND_RD_ERROR             (1L<<6)
4549 #define BNX2_MQ_COMMAND_IDB_CFG_ERROR            (1L<<7)
4550 #define BNX2_MQ_COMMAND_IDB_OVERFLOW             (1L<<10)
4551 #define BNX2_MQ_COMMAND_NO_BIN_ERROR             (1L<<11)
4552 #define BNX2_MQ_COMMAND_NO_MAP_ERROR             (1L<<12)
4553 
4554 #define BNX2_MQ_STATUS                  0x00003c04
4555 #define BNX2_MQ_STATUS_CTX_ACCESS_STAT           (1L<<16)
4556 #define BNX2_MQ_STATUS_CTX_ACCESS64_STAT         (1L<<17)
4557 #define BNX2_MQ_STATUS_PCI_STALL_STAT            (1L<<18)
4558 #define BNX2_MQ_STATUS_IDB_OFLOW_STAT            (1L<<19)
4559 
4560 #define BNX2_MQ_CONFIG                  0x00003c08
4561 #define BNX2_MQ_CONFIG_TX_HIGH_PRI           (1L<<0)
4562 #define BNX2_MQ_CONFIG_HALT_DIS              (1L<<1)
4563 #define BNX2_MQ_CONFIG_BIN_MQ_MODE           (1L<<2)
4564 #define BNX2_MQ_CONFIG_DIS_IDB_DROP          (1L<<3)
4565 #define BNX2_MQ_CONFIG_KNL_BYP_BLK_SIZE          (0x7L<<4)
4566 #define BNX2_MQ_CONFIG_KNL_BYP_BLK_SIZE_256      (0L<<4)
4567 #define BNX2_MQ_CONFIG_KNL_BYP_BLK_SIZE_512      (1L<<4)
4568 #define BNX2_MQ_CONFIG_KNL_BYP_BLK_SIZE_1K       (2L<<4)
4569 #define BNX2_MQ_CONFIG_KNL_BYP_BLK_SIZE_2K       (3L<<4)
4570 #define BNX2_MQ_CONFIG_KNL_BYP_BLK_SIZE_4K       (4L<<4)
4571 #define BNX2_MQ_CONFIG_MAX_DEPTH             (0x7fL<<8)
4572 #define BNX2_MQ_CONFIG_CUR_DEPTH             (0x7fL<<20)
4573 
4574 #define BNX2_MQ_ENQUEUE1                0x00003c0c
4575 #define BNX2_MQ_ENQUEUE1_OFFSET              (0x3fL<<2)
4576 #define BNX2_MQ_ENQUEUE1_CID                 (0x3fffL<<8)
4577 #define BNX2_MQ_ENQUEUE1_BYTE_MASK           (0xfL<<24)
4578 #define BNX2_MQ_ENQUEUE1_KNL_MODE            (1L<<28)
4579 
4580 #define BNX2_MQ_ENQUEUE2                0x00003c10
4581 #define BNX2_MQ_BAD_WR_ADDR             0x00003c14
4582 #define BNX2_MQ_BAD_RD_ADDR             0x00003c18
4583 #define BNX2_MQ_KNL_BYP_WIND_START          0x00003c1c
4584 #define BNX2_MQ_KNL_BYP_WIND_START_VALUE         (0xfffffL<<12)
4585 
4586 #define BNX2_MQ_KNL_WIND_END                0x00003c20
4587 #define BNX2_MQ_KNL_WIND_END_VALUE           (0xffffffL<<8)
4588 
4589 #define BNX2_MQ_KNL_WRITE_MASK1             0x00003c24
4590 #define BNX2_MQ_KNL_TX_MASK1                0x00003c28
4591 #define BNX2_MQ_KNL_CMD_MASK1               0x00003c2c
4592 #define BNX2_MQ_KNL_COND_ENQUEUE_MASK1          0x00003c30
4593 #define BNX2_MQ_KNL_RX_V2P_MASK1            0x00003c34
4594 #define BNX2_MQ_KNL_WRITE_MASK2             0x00003c38
4595 #define BNX2_MQ_KNL_TX_MASK2                0x00003c3c
4596 #define BNX2_MQ_KNL_CMD_MASK2               0x00003c40
4597 #define BNX2_MQ_KNL_COND_ENQUEUE_MASK2          0x00003c44
4598 #define BNX2_MQ_KNL_RX_V2P_MASK2            0x00003c48
4599 #define BNX2_MQ_KNL_BYP_WRITE_MASK1         0x00003c4c
4600 #define BNX2_MQ_KNL_BYP_TX_MASK1            0x00003c50
4601 #define BNX2_MQ_KNL_BYP_CMD_MASK1           0x00003c54
4602 #define BNX2_MQ_KNL_BYP_COND_ENQUEUE_MASK1      0x00003c58
4603 #define BNX2_MQ_KNL_BYP_RX_V2P_MASK1            0x00003c5c
4604 #define BNX2_MQ_KNL_BYP_WRITE_MASK2         0x00003c60
4605 #define BNX2_MQ_KNL_BYP_TX_MASK2            0x00003c64
4606 #define BNX2_MQ_KNL_BYP_CMD_MASK2           0x00003c68
4607 #define BNX2_MQ_KNL_BYP_COND_ENQUEUE_MASK2      0x00003c6c
4608 #define BNX2_MQ_KNL_BYP_RX_V2P_MASK2            0x00003c70
4609 #define BNX2_MQ_MEM_WR_ADDR             0x00003c74
4610 #define BNX2_MQ_MEM_WR_ADDR_VALUE            (0x3fL<<0)
4611 
4612 #define BNX2_MQ_MEM_WR_DATA0                0x00003c78
4613 #define BNX2_MQ_MEM_WR_DATA0_VALUE           (0xffffffffL<<0)
4614 
4615 #define BNX2_MQ_MEM_WR_DATA1                0x00003c7c
4616 #define BNX2_MQ_MEM_WR_DATA1_VALUE           (0xffffffffL<<0)
4617 
4618 #define BNX2_MQ_MEM_WR_DATA2                0x00003c80
4619 #define BNX2_MQ_MEM_WR_DATA2_VALUE           (0x3fffffffL<<0)
4620 #define BNX2_MQ_MEM_WR_DATA2_VALUE_XI            (0x7fffffffL<<0)
4621 
4622 #define BNX2_MQ_MEM_RD_ADDR             0x00003c84
4623 #define BNX2_MQ_MEM_RD_ADDR_VALUE            (0x3fL<<0)
4624 
4625 #define BNX2_MQ_MEM_RD_DATA0                0x00003c88
4626 #define BNX2_MQ_MEM_RD_DATA0_VALUE           (0xffffffffL<<0)
4627 
4628 #define BNX2_MQ_MEM_RD_DATA1                0x00003c8c
4629 #define BNX2_MQ_MEM_RD_DATA1_VALUE           (0xffffffffL<<0)
4630 
4631 #define BNX2_MQ_MEM_RD_DATA2                0x00003c90
4632 #define BNX2_MQ_MEM_RD_DATA2_VALUE           (0x3fffffffL<<0)
4633 #define BNX2_MQ_MEM_RD_DATA2_VALUE_XI            (0x7fffffffL<<0)
4634 
4635 #define BNX2_MQ_MAP_L2_3                0x00003d2c
4636 #define BNX2_MQ_MAP_L2_3_MQ_OFFSET           (0xffL<<0)
4637 #define BNX2_MQ_MAP_L2_3_SZ              (0x3L<<8)
4638 #define BNX2_MQ_MAP_L2_3_CTX_OFFSET          (0x2ffL<<10)
4639 #define BNX2_MQ_MAP_L2_3_BIN_OFFSET          (0x7L<<23)
4640 #define BNX2_MQ_MAP_L2_3_ARM                 (0x3L<<26)
4641 #define BNX2_MQ_MAP_L2_3_ENA                 (0x1L<<31)
4642 #define BNX2_MQ_MAP_L2_3_DEFAULT             0x82004646
4643 
4644 #define BNX2_MQ_MAP_L2_5                0x00003d34
4645 #define BNX2_MQ_MAP_L2_5_ARM                 (0x3L<<26)
4646 
4647 /*
4648  *  tsch_reg definition
4649  *  offset: 0x4c00
4650  */
4651 #define BNX2_TSCH_TSS_CFG               0x00004c1c
4652 #define BNX2_TSCH_TSS_CFG_TSS_START_CID          (0x7ffL<<8)
4653 #define BNX2_TSCH_TSS_CFG_NUM_OF_TSS_CON         (0xfL<<24)
4654 
4655 
4656 
4657 /*
4658  *  tbdr_reg definition
4659  *  offset: 0x5000
4660  */
4661 #define BNX2_TBDR_COMMAND               0x00005000
4662 #define BNX2_TBDR_COMMAND_ENABLE             (1L<<0)
4663 #define BNX2_TBDR_COMMAND_SOFT_RST           (1L<<1)
4664 #define BNX2_TBDR_COMMAND_MSTR_ABORT             (1L<<4)
4665 
4666 #define BNX2_TBDR_STATUS                0x00005004
4667 #define BNX2_TBDR_STATUS_DMA_WAIT            (1L<<0)
4668 #define BNX2_TBDR_STATUS_FTQ_WAIT            (1L<<1)
4669 #define BNX2_TBDR_STATUS_FIFO_OVERFLOW           (1L<<2)
4670 #define BNX2_TBDR_STATUS_FIFO_UNDERFLOW          (1L<<3)
4671 #define BNX2_TBDR_STATUS_SEARCHMISS_ERROR        (1L<<4)
4672 #define BNX2_TBDR_STATUS_FTQ_ENTRY_CNT           (1L<<5)
4673 #define BNX2_TBDR_STATUS_BURST_CNT           (1L<<6)
4674 
4675 #define BNX2_TBDR_CONFIG                0x00005008
4676 #define BNX2_TBDR_CONFIG_MAX_BDS             (0xffL<<0)
4677 #define BNX2_TBDR_CONFIG_SWAP_MODE           (1L<<8)
4678 #define BNX2_TBDR_CONFIG_PRIORITY            (1L<<9)
4679 #define BNX2_TBDR_CONFIG_CACHE_NEXT_PAGE_PTRS        (1L<<10)
4680 #define BNX2_TBDR_CONFIG_PAGE_SIZE           (0xfL<<24)
4681 #define BNX2_TBDR_CONFIG_PAGE_SIZE_256           (0L<<24)
4682 #define BNX2_TBDR_CONFIG_PAGE_SIZE_512           (1L<<24)
4683 #define BNX2_TBDR_CONFIG_PAGE_SIZE_1K            (2L<<24)
4684 #define BNX2_TBDR_CONFIG_PAGE_SIZE_2K            (3L<<24)
4685 #define BNX2_TBDR_CONFIG_PAGE_SIZE_4K            (4L<<24)
4686 #define BNX2_TBDR_CONFIG_PAGE_SIZE_8K            (5L<<24)
4687 #define BNX2_TBDR_CONFIG_PAGE_SIZE_16K           (6L<<24)
4688 #define BNX2_TBDR_CONFIG_PAGE_SIZE_32K           (7L<<24)
4689 #define BNX2_TBDR_CONFIG_PAGE_SIZE_64K           (8L<<24)
4690 #define BNX2_TBDR_CONFIG_PAGE_SIZE_128K          (9L<<24)
4691 #define BNX2_TBDR_CONFIG_PAGE_SIZE_256K          (10L<<24)
4692 #define BNX2_TBDR_CONFIG_PAGE_SIZE_512K          (11L<<24)
4693 #define BNX2_TBDR_CONFIG_PAGE_SIZE_1M            (12L<<24)
4694 
4695 #define BNX2_TBDR_DEBUG_VECT_PEEK           0x0000500c
4696 #define BNX2_TBDR_DEBUG_VECT_PEEK_1_VALUE        (0x7ffL<<0)
4697 #define BNX2_TBDR_DEBUG_VECT_PEEK_1_PEEK_EN      (1L<<11)
4698 #define BNX2_TBDR_DEBUG_VECT_PEEK_1_SEL          (0xfL<<12)
4699 #define BNX2_TBDR_DEBUG_VECT_PEEK_2_VALUE        (0x7ffL<<16)
4700 #define BNX2_TBDR_DEBUG_VECT_PEEK_2_PEEK_EN      (1L<<27)
4701 #define BNX2_TBDR_DEBUG_VECT_PEEK_2_SEL          (0xfL<<28)
4702 
4703 #define BNX2_TBDR_CKSUM_ERROR_STATUS            0x00005010
4704 #define BNX2_TBDR_CKSUM_ERROR_STATUS_CALCULATED      (0xffffL<<0)
4705 #define BNX2_TBDR_CKSUM_ERROR_STATUS_EXPECTED        (0xffffL<<16)
4706 
4707 #define BNX2_TBDR_TBDRQ                 0x000053c0
4708 #define BNX2_TBDR_FTQ_CMD               0x000053f8
4709 #define BNX2_TBDR_FTQ_CMD_OFFSET             (0x3ffL<<0)
4710 #define BNX2_TBDR_FTQ_CMD_WR_TOP             (1L<<10)
4711 #define BNX2_TBDR_FTQ_CMD_WR_TOP_0           (0L<<10)
4712 #define BNX2_TBDR_FTQ_CMD_WR_TOP_1           (1L<<10)
4713 #define BNX2_TBDR_FTQ_CMD_SFT_RESET          (1L<<25)
4714 #define BNX2_TBDR_FTQ_CMD_RD_DATA            (1L<<26)
4715 #define BNX2_TBDR_FTQ_CMD_ADD_INTERVEN           (1L<<27)
4716 #define BNX2_TBDR_FTQ_CMD_ADD_DATA           (1L<<28)
4717 #define BNX2_TBDR_FTQ_CMD_INTERVENE_CLR          (1L<<29)
4718 #define BNX2_TBDR_FTQ_CMD_POP                (1L<<30)
4719 #define BNX2_TBDR_FTQ_CMD_BUSY               (1L<<31)
4720 
4721 #define BNX2_TBDR_FTQ_CTL               0x000053fc
4722 #define BNX2_TBDR_FTQ_CTL_INTERVENE          (1L<<0)
4723 #define BNX2_TBDR_FTQ_CTL_OVERFLOW           (1L<<1)
4724 #define BNX2_TBDR_FTQ_CTL_FORCE_INTERVENE        (1L<<2)
4725 #define BNX2_TBDR_FTQ_CTL_MAX_DEPTH          (0x3ffL<<12)
4726 #define BNX2_TBDR_FTQ_CTL_CUR_DEPTH          (0x3ffL<<22)
4727 
4728 
4729 
4730 /*
4731  *  tdma_reg definition
4732  *  offset: 0x5c00
4733  */
4734 #define BNX2_TDMA_COMMAND               0x00005c00
4735 #define BNX2_TDMA_COMMAND_ENABLED            (1L<<0)
4736 #define BNX2_TDMA_COMMAND_MASTER_ABORT           (1L<<4)
4737 #define BNX2_TDMA_COMMAND_CS16_ERR           (1L<<5)
4738 #define BNX2_TDMA_COMMAND_BAD_L2_LENGTH_ABORT        (1L<<7)
4739 #define BNX2_TDMA_COMMAND_MASK_CS1           (1L<<20)
4740 #define BNX2_TDMA_COMMAND_MASK_CS2           (1L<<21)
4741 #define BNX2_TDMA_COMMAND_MASK_CS3           (1L<<22)
4742 #define BNX2_TDMA_COMMAND_MASK_CS4           (1L<<23)
4743 #define BNX2_TDMA_COMMAND_FORCE_ILOCK_CKERR      (1L<<24)
4744 #define BNX2_TDMA_COMMAND_OFIFO_CLR          (1L<<30)
4745 #define BNX2_TDMA_COMMAND_IFIFO_CLR          (1L<<31)
4746 
4747 #define BNX2_TDMA_STATUS                0x00005c04
4748 #define BNX2_TDMA_STATUS_DMA_WAIT            (1L<<0)
4749 #define BNX2_TDMA_STATUS_PAYLOAD_WAIT            (1L<<1)
4750 #define BNX2_TDMA_STATUS_PATCH_FTQ_WAIT          (1L<<2)
4751 #define BNX2_TDMA_STATUS_LOCK_WAIT           (1L<<3)
4752 #define BNX2_TDMA_STATUS_FTQ_ENTRY_CNT           (1L<<16)
4753 #define BNX2_TDMA_STATUS_BURST_CNT           (1L<<17)
4754 #define BNX2_TDMA_STATUS_MAX_IFIFO_DEPTH         (0x3fL<<20)
4755 #define BNX2_TDMA_STATUS_OFIFO_OVERFLOW          (1L<<30)
4756 #define BNX2_TDMA_STATUS_IFIFO_OVERFLOW          (1L<<31)
4757 
4758 #define BNX2_TDMA_CONFIG                0x00005c08
4759 #define BNX2_TDMA_CONFIG_ONE_DMA             (1L<<0)
4760 #define BNX2_TDMA_CONFIG_ONE_RECORD          (1L<<1)
4761 #define BNX2_TDMA_CONFIG_NUM_DMA_CHAN            (0x3L<<2)
4762 #define BNX2_TDMA_CONFIG_NUM_DMA_CHAN_0          (0L<<2)
4763 #define BNX2_TDMA_CONFIG_NUM_DMA_CHAN_1          (1L<<2)
4764 #define BNX2_TDMA_CONFIG_NUM_DMA_CHAN_2          (2L<<2)
4765 #define BNX2_TDMA_CONFIG_NUM_DMA_CHAN_3          (3L<<2)
4766 #define BNX2_TDMA_CONFIG_LIMIT_SZ            (0xfL<<4)
4767 #define BNX2_TDMA_CONFIG_LIMIT_SZ_64             (0L<<4)
4768 #define BNX2_TDMA_CONFIG_LIMIT_SZ_128            (0x4L<<4)
4769 #define BNX2_TDMA_CONFIG_LIMIT_SZ_256            (0x6L<<4)
4770 #define BNX2_TDMA_CONFIG_LIMIT_SZ_512            (0x8L<<4)
4771 #define BNX2_TDMA_CONFIG_LINE_SZ             (0xfL<<8)
4772 #define BNX2_TDMA_CONFIG_LINE_SZ_64          (0L<<8)
4773 #define BNX2_TDMA_CONFIG_LINE_SZ_128             (4L<<8)
4774 #define BNX2_TDMA_CONFIG_LINE_SZ_256             (6L<<8)
4775 #define BNX2_TDMA_CONFIG_LINE_SZ_512             (8L<<8)
4776 #define BNX2_TDMA_CONFIG_ALIGN_ENA           (1L<<15)
4777 #define BNX2_TDMA_CONFIG_CHK_L2_BD           (1L<<16)
4778 #define BNX2_TDMA_CONFIG_CMPL_ENTRY          (1L<<17)
4779 #define BNX2_TDMA_CONFIG_OFIFO_CMP           (1L<<19)
4780 #define BNX2_TDMA_CONFIG_OFIFO_CMP_3             (0L<<19)
4781 #define BNX2_TDMA_CONFIG_OFIFO_CMP_2             (1L<<19)
4782 #define BNX2_TDMA_CONFIG_FIFO_CMP            (0xfL<<20)
4783 #define BNX2_TDMA_CONFIG_IFIFO_DEPTH_XI          (0x7L<<20)
4784 #define BNX2_TDMA_CONFIG_IFIFO_DEPTH_0_XI        (0L<<20)
4785 #define BNX2_TDMA_CONFIG_IFIFO_DEPTH_4_XI        (1L<<20)
4786 #define BNX2_TDMA_CONFIG_IFIFO_DEPTH_8_XI        (2L<<20)
4787 #define BNX2_TDMA_CONFIG_IFIFO_DEPTH_16_XI       (3L<<20)
4788 #define BNX2_TDMA_CONFIG_IFIFO_DEPTH_32_XI       (4L<<20)
4789 #define BNX2_TDMA_CONFIG_IFIFO_DEPTH_64_XI       (5L<<20)
4790 #define BNX2_TDMA_CONFIG_FIFO_CMP_EN_XI          (1L<<23)
4791 #define BNX2_TDMA_CONFIG_BYTES_OST_XI            (0x7L<<24)
4792 #define BNX2_TDMA_CONFIG_BYTES_OST_512_XI        (0L<<24)
4793 #define BNX2_TDMA_CONFIG_BYTES_OST_1024_XI       (1L<<24)
4794 #define BNX2_TDMA_CONFIG_BYTES_OST_2048_XI       (2L<<24)
4795 #define BNX2_TDMA_CONFIG_BYTES_OST_4096_XI       (3L<<24)
4796 #define BNX2_TDMA_CONFIG_BYTES_OST_8192_XI       (4L<<24)
4797 #define BNX2_TDMA_CONFIG_BYTES_OST_16384_XI      (5L<<24)
4798 #define BNX2_TDMA_CONFIG_HC_BYPASS_XI            (1L<<27)
4799 #define BNX2_TDMA_CONFIG_LCL_MRRS_XI             (0x7L<<28)
4800 #define BNX2_TDMA_CONFIG_LCL_MRRS_128_XI         (0L<<28)
4801 #define BNX2_TDMA_CONFIG_LCL_MRRS_256_XI         (1L<<28)
4802 #define BNX2_TDMA_CONFIG_LCL_MRRS_512_XI         (2L<<28)
4803 #define BNX2_TDMA_CONFIG_LCL_MRRS_1024_XI        (3L<<28)
4804 #define BNX2_TDMA_CONFIG_LCL_MRRS_2048_XI        (4L<<28)
4805 #define BNX2_TDMA_CONFIG_LCL_MRRS_4096_XI        (5L<<28)
4806 #define BNX2_TDMA_CONFIG_LCL_MRRS_EN_XI          (1L<<31)
4807 
4808 #define BNX2_TDMA_PAYLOAD_PROD              0x00005c0c
4809 #define BNX2_TDMA_PAYLOAD_PROD_VALUE             (0x1fffL<<3)
4810 
4811 #define BNX2_TDMA_DBG_WATCHDOG              0x00005c10
4812 #define BNX2_TDMA_DBG_TRIGGER               0x00005c14
4813 #define BNX2_TDMA_DMAD_FSM              0x00005c80
4814 #define BNX2_TDMA_DMAD_FSM_BD_INVLD          (1L<<0)
4815 #define BNX2_TDMA_DMAD_FSM_PUSH              (0xfL<<4)
4816 #define BNX2_TDMA_DMAD_FSM_ARB_TBDC          (0x3L<<8)
4817 #define BNX2_TDMA_DMAD_FSM_ARB_CTX           (1L<<12)
4818 #define BNX2_TDMA_DMAD_FSM_DR_INTF           (1L<<16)
4819 #define BNX2_TDMA_DMAD_FSM_DMAD              (0x7L<<20)
4820 #define BNX2_TDMA_DMAD_FSM_BD                (0xfL<<24)
4821 
4822 #define BNX2_TDMA_DMAD_STATUS               0x00005c84
4823 #define BNX2_TDMA_DMAD_STATUS_RHOLD_PUSH_ENTRY       (0x3L<<0)
4824 #define BNX2_TDMA_DMAD_STATUS_RHOLD_DMAD_ENTRY       (0x3L<<4)
4825 #define BNX2_TDMA_DMAD_STATUS_RHOLD_BD_ENTRY         (0x3L<<8)
4826 #define BNX2_TDMA_DMAD_STATUS_IFTQ_ENUM          (0xfL<<12)
4827 
4828 #define BNX2_TDMA_DR_INTF_FSM               0x00005c88
4829 #define BNX2_TDMA_DR_INTF_FSM_L2_COMP            (0x3L<<0)
4830 #define BNX2_TDMA_DR_INTF_FSM_TPATQ          (0x7L<<4)
4831 #define BNX2_TDMA_DR_INTF_FSM_TPBUF          (0x3L<<8)
4832 #define BNX2_TDMA_DR_INTF_FSM_DR_BUF             (0x7L<<12)
4833 #define BNX2_TDMA_DR_INTF_FSM_DMAD           (0x7L<<16)
4834 
4835 #define BNX2_TDMA_DR_INTF_STATUS            0x00005c8c
4836 #define BNX2_TDMA_DR_INTF_STATUS_HOLE_PHASE      (0x7L<<0)
4837 #define BNX2_TDMA_DR_INTF_STATUS_DATA_AVAIL      (0x3L<<4)
4838 #define BNX2_TDMA_DR_INTF_STATUS_SHIFT_ADDR      (0x7L<<8)
4839 #define BNX2_TDMA_DR_INTF_STATUS_NXT_PNTR        (0xfL<<12)
4840 #define BNX2_TDMA_DR_INTF_STATUS_BYTE_COUNT      (0x7L<<16)
4841 
4842 #define BNX2_TDMA_PUSH_FSM              0x00005c90
4843 #define BNX2_TDMA_BD_IF_DEBUG               0x00005c94
4844 #define BNX2_TDMA_DMAD_IF_DEBUG             0x00005c98
4845 #define BNX2_TDMA_CTX_IF_DEBUG              0x00005c9c
4846 #define BNX2_TDMA_TPBUF_IF_DEBUG            0x00005ca0
4847 #define BNX2_TDMA_DR_IF_DEBUG               0x00005ca4
4848 #define BNX2_TDMA_TPATQ_IF_DEBUG            0x00005ca8
4849 #define BNX2_TDMA_TDMA_ILOCK_CKSUM          0x00005cac
4850 #define BNX2_TDMA_TDMA_ILOCK_CKSUM_CALCULATED        (0xffffL<<0)
4851 #define BNX2_TDMA_TDMA_ILOCK_CKSUM_EXPECTED      (0xffffL<<16)
4852 
4853 #define BNX2_TDMA_TDMA_PCIE_CKSUM           0x00005cb0
4854 #define BNX2_TDMA_TDMA_PCIE_CKSUM_CALCULATED         (0xffffL<<0)
4855 #define BNX2_TDMA_TDMA_PCIE_CKSUM_EXPECTED       (0xffffL<<16)
4856 
4857 #define BNX2_TDMA_TDMAQ                 0x00005fc0
4858 #define BNX2_TDMA_FTQ_CMD               0x00005ff8
4859 #define BNX2_TDMA_FTQ_CMD_OFFSET             (0x3ffL<<0)
4860 #define BNX2_TDMA_FTQ_CMD_WR_TOP             (1L<<10)
4861 #define BNX2_TDMA_FTQ_CMD_WR_TOP_0           (0L<<10)
4862 #define BNX2_TDMA_FTQ_CMD_WR_TOP_1           (1L<<10)
4863 #define BNX2_TDMA_FTQ_CMD_SFT_RESET          (1L<<25)
4864 #define BNX2_TDMA_FTQ_CMD_RD_DATA            (1L<<26)
4865 #define BNX2_TDMA_FTQ_CMD_ADD_INTERVEN           (1L<<27)
4866 #define BNX2_TDMA_FTQ_CMD_ADD_DATA           (1L<<28)
4867 #define BNX2_TDMA_FTQ_CMD_INTERVENE_CLR          (1L<<29)
4868 #define BNX2_TDMA_FTQ_CMD_POP                (1L<<30)
4869 #define BNX2_TDMA_FTQ_CMD_BUSY               (1L<<31)
4870 
4871 #define BNX2_TDMA_FTQ_CTL               0x00005ffc
4872 #define BNX2_TDMA_FTQ_CTL_INTERVENE          (1L<<0)
4873 #define BNX2_TDMA_FTQ_CTL_OVERFLOW           (1L<<1)
4874 #define BNX2_TDMA_FTQ_CTL_FORCE_INTERVENE        (1L<<2)
4875 #define BNX2_TDMA_FTQ_CTL_MAX_DEPTH          (0x3ffL<<12)
4876 #define BNX2_TDMA_FTQ_CTL_CUR_DEPTH          (0x3ffL<<22)
4877 
4878 
4879 
4880 /*
4881  *  hc_reg definition
4882  *  offset: 0x6800
4883  */
4884 #define BNX2_HC_COMMAND                 0x00006800
4885 #define BNX2_HC_COMMAND_ENABLE               (1L<<0)
4886 #define BNX2_HC_COMMAND_SKIP_ABORT           (1L<<4)
4887 #define BNX2_HC_COMMAND_COAL_NOW             (1L<<16)
4888 #define BNX2_HC_COMMAND_COAL_NOW_WO_INT          (1L<<17)
4889 #define BNX2_HC_COMMAND_STATS_NOW            (1L<<18)
4890 #define BNX2_HC_COMMAND_FORCE_INT            (0x3L<<19)
4891 #define BNX2_HC_COMMAND_FORCE_INT_NULL           (0L<<19)
4892 #define BNX2_HC_COMMAND_FORCE_INT_HIGH           (1L<<19)
4893 #define BNX2_HC_COMMAND_FORCE_INT_LOW            (2L<<19)
4894 #define BNX2_HC_COMMAND_FORCE_INT_FREE           (3L<<19)
4895 #define BNX2_HC_COMMAND_CLR_STAT_NOW             (1L<<21)
4896 #define BNX2_HC_COMMAND_MAIN_PWR_INT             (1L<<22)
4897 #define BNX2_HC_COMMAND_COAL_ON_NEXT_EVENT       (1L<<27)
4898 
4899 #define BNX2_HC_STATUS                  0x00006804
4900 #define BNX2_HC_STATUS_MASTER_ABORT          (1L<<0)
4901 #define BNX2_HC_STATUS_PARITY_ERROR_STATE        (1L<<1)
4902 #define BNX2_HC_STATUS_PCI_CLK_CNT_STAT          (1L<<16)
4903 #define BNX2_HC_STATUS_CORE_CLK_CNT_STAT         (1L<<17)
4904 #define BNX2_HC_STATUS_NUM_STATUS_BLOCKS_STAT        (1L<<18)
4905 #define BNX2_HC_STATUS_NUM_INT_GEN_STAT          (1L<<19)
4906 #define BNX2_HC_STATUS_NUM_INT_MBOX_WR_STAT      (1L<<20)
4907 #define BNX2_HC_STATUS_CORE_CLKS_TO_HW_INTACK_STAT   (1L<<23)
4908 #define BNX2_HC_STATUS_CORE_CLKS_TO_SW_INTACK_STAT   (1L<<24)
4909 #define BNX2_HC_STATUS_CORE_CLKS_DURING_SW_INTACK_STAT   (1L<<25)
4910 
4911 #define BNX2_HC_CONFIG                  0x00006808
4912 #define BNX2_HC_CONFIG_COLLECT_STATS             (1L<<0)
4913 #define BNX2_HC_CONFIG_RX_TMR_MODE           (1L<<1)
4914 #define BNX2_HC_CONFIG_TX_TMR_MODE           (1L<<2)
4915 #define BNX2_HC_CONFIG_COM_TMR_MODE          (1L<<3)
4916 #define BNX2_HC_CONFIG_CMD_TMR_MODE          (1L<<4)
4917 #define BNX2_HC_CONFIG_STATISTIC_PRIORITY        (1L<<5)
4918 #define BNX2_HC_CONFIG_STATUS_PRIORITY           (1L<<6)
4919 #define BNX2_HC_CONFIG_STAT_MEM_ADDR             (0xffL<<8)
4920 #define BNX2_HC_CONFIG_PER_MODE              (1L<<16)
4921 #define BNX2_HC_CONFIG_ONE_SHOT              (1L<<17)
4922 #define BNX2_HC_CONFIG_USE_INT_PARAM             (1L<<18)
4923 #define BNX2_HC_CONFIG_SET_MASK_AT_RD            (1L<<19)
4924 #define BNX2_HC_CONFIG_PER_COLLECT_LIMIT         (0xfL<<20)
4925 #define BNX2_HC_CONFIG_SB_ADDR_INC           (0x7L<<24)
4926 #define BNX2_HC_CONFIG_SB_ADDR_INC_64B           (0L<<24)
4927 #define BNX2_HC_CONFIG_SB_ADDR_INC_128B          (1L<<24)
4928 #define BNX2_HC_CONFIG_SB_ADDR_INC_256B          (2L<<24)
4929 #define BNX2_HC_CONFIG_SB_ADDR_INC_512B          (3L<<24)
4930 #define BNX2_HC_CONFIG_SB_ADDR_INC_1024B         (4L<<24)
4931 #define BNX2_HC_CONFIG_SB_ADDR_INC_2048B         (5L<<24)
4932 #define BNX2_HC_CONFIG_SB_ADDR_INC_4096B         (6L<<24)
4933 #define BNX2_HC_CONFIG_SB_ADDR_INC_8192B         (7L<<24)
4934 #define BNX2_HC_CONFIG_GEN_STAT_AVG_INTR         (1L<<29)
4935 #define BNX2_HC_CONFIG_UNMASK_ALL            (1L<<30)
4936 #define BNX2_HC_CONFIG_TX_SEL                (1L<<31)
4937 
4938 #define BNX2_HC_ATTN_BITS_ENABLE            0x0000680c
4939 #define BNX2_HC_STATUS_ADDR_L               0x00006810
4940 #define BNX2_HC_STATUS_ADDR_H               0x00006814
4941 #define BNX2_HC_STATISTICS_ADDR_L           0x00006818
4942 #define BNX2_HC_STATISTICS_ADDR_H           0x0000681c
4943 #define BNX2_HC_TX_QUICK_CONS_TRIP          0x00006820
4944 #define BNX2_HC_TX_QUICK_CONS_TRIP_VALUE         (0xffL<<0)
4945 #define BNX2_HC_TX_QUICK_CONS_TRIP_INT           (0xffL<<16)
4946 
4947 #define BNX2_HC_COMP_PROD_TRIP              0x00006824
4948 #define BNX2_HC_COMP_PROD_TRIP_VALUE             (0xffL<<0)
4949 #define BNX2_HC_COMP_PROD_TRIP_INT           (0xffL<<16)
4950 
4951 #define BNX2_HC_RX_QUICK_CONS_TRIP          0x00006828
4952 #define BNX2_HC_RX_QUICK_CONS_TRIP_VALUE         (0xffL<<0)
4953 #define BNX2_HC_RX_QUICK_CONS_TRIP_INT           (0xffL<<16)
4954 
4955 #define BNX2_HC_RX_TICKS                0x0000682c
4956 #define BNX2_HC_RX_TICKS_VALUE               (0x3ffL<<0)
4957 #define BNX2_HC_RX_TICKS_INT                 (0x3ffL<<16)
4958 
4959 #define BNX2_HC_TX_TICKS                0x00006830
4960 #define BNX2_HC_TX_TICKS_VALUE               (0x3ffL<<0)
4961 #define BNX2_HC_TX_TICKS_INT                 (0x3ffL<<16)
4962 
4963 #define BNX2_HC_COM_TICKS               0x00006834
4964 #define BNX2_HC_COM_TICKS_VALUE              (0x3ffL<<0)
4965 #define BNX2_HC_COM_TICKS_INT                (0x3ffL<<16)
4966 
4967 #define BNX2_HC_CMD_TICKS               0x00006838
4968 #define BNX2_HC_CMD_TICKS_VALUE              (0x3ffL<<0)
4969 #define BNX2_HC_CMD_TICKS_INT                (0x3ffL<<16)
4970 
4971 #define BNX2_HC_PERIODIC_TICKS              0x0000683c
4972 #define BNX2_HC_PERIODIC_TICKS_HC_PERIODIC_TICKS     (0xffffL<<0)
4973 #define BNX2_HC_PERIODIC_TICKS_HC_INT_PERIODIC_TICKS     (0xffffL<<16)
4974 
4975 #define BNX2_HC_STAT_COLLECT_TICKS          0x00006840
4976 #define BNX2_HC_STAT_COLLECT_TICKS_HC_STAT_COLL_TICKS    (0xffL<<4)
4977 
4978 #define BNX2_HC_STATS_TICKS             0x00006844
4979 #define BNX2_HC_STATS_TICKS_HC_STAT_TICKS        (0xffffL<<8)
4980 
4981 #define BNX2_HC_STATS_INTERRUPT_STATUS          0x00006848
4982 #define BNX2_HC_STATS_INTERRUPT_STATUS_SB_STATUS     (0x1ffL<<0)
4983 #define BNX2_HC_STATS_INTERRUPT_STATUS_INT_STATUS    (0x1ffL<<16)
4984 
4985 #define BNX2_HC_STAT_MEM_DATA               0x0000684c
4986 #define BNX2_HC_STAT_GEN_SEL_0              0x00006850
4987 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0         (0x7fL<<0)
4988 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_RXP_STAT0   (0L<<0)
4989 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_RXP_STAT1   (1L<<0)
4990 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_RXP_STAT2   (2L<<0)
4991 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_RXP_STAT3   (3L<<0)
4992 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_RXP_STAT4   (4L<<0)
4993 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_RXP_STAT5   (5L<<0)
4994 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_RXP_STAT6   (6L<<0)
4995 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_RXP_STAT7   (7L<<0)
4996 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_RXP_STAT8   (8L<<0)
4997 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_RXP_STAT9   (9L<<0)
4998 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_RXP_STAT10  (10L<<0)
4999 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_RXP_STAT11  (11L<<0)
5000 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_TXP_STAT0   (12L<<0)
5001 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_TXP_STAT1   (13L<<0)
5002 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_TXP_STAT2   (14L<<0)
5003 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_TXP_STAT3   (15L<<0)
5004 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_TXP_STAT4   (16L<<0)
5005 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_TXP_STAT5   (17L<<0)
5006 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_TXP_STAT6   (18L<<0)
5007 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_TXP_STAT7   (19L<<0)
5008 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_COM_STAT0   (20L<<0)
5009 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_COM_STAT1   (21L<<0)
5010 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_COM_STAT2   (22L<<0)
5011 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_COM_STAT3   (23L<<0)
5012 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_COM_STAT4   (24L<<0)
5013 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_COM_STAT5   (25L<<0)
5014 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_COM_STAT6   (26L<<0)
5015 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_COM_STAT7   (27L<<0)
5016 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_COM_STAT8   (28L<<0)
5017 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_COM_STAT9   (29L<<0)
5018 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_COM_STAT10  (30L<<0)
5019 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_COM_STAT11  (31L<<0)
5020 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_TPAT_STAT0  (32L<<0)
5021 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_TPAT_STAT1  (33L<<0)
5022 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_TPAT_STAT2  (34L<<0)
5023 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_TPAT_STAT3  (35L<<0)
5024 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_CP_STAT0    (36L<<0)
5025 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_CP_STAT1    (37L<<0)
5026 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_CP_STAT2    (38L<<0)
5027 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_CP_STAT3    (39L<<0)
5028 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_CP_STAT4    (40L<<0)
5029 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_CP_STAT5    (41L<<0)
5030 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_CP_STAT6    (42L<<0)
5031 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_CP_STAT7    (43L<<0)
5032 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_MCP_STAT0   (44L<<0)
5033 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_MCP_STAT1   (45L<<0)
5034 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_MCP_STAT2   (46L<<0)
5035 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_MCP_STAT3   (47L<<0)
5036 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_MCP_STAT4   (48L<<0)
5037 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_MCP_STAT5   (49L<<0)
5038 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_MCP_STAT6   (50L<<0)
5039 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_MCP_STAT7   (51L<<0)
5040 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_PCI_CLK_CNT     (52L<<0)
5041 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_CORE_CLK_CNT    (53L<<0)
5042 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_NUM_STATUS_BLOCKS    (54L<<0)
5043 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_NUM_INT_GEN  (55L<<0)
5044 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_NUM_INT_MBOX_WR  (56L<<0)
5045 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_CORE_CLKS_TO_HW_INTACK   (59L<<0)
5046 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_CORE_CLKS_TO_SW_INTACK   (60L<<0)
5047 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_CORE_CLKS_DURING_SW_INTACK   (61L<<0)
5048 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_TSCH_CMD_CNT    (62L<<0)
5049 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_TSCH_SLOT_CNT   (63L<<0)
5050 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_CSCH_CMD_CNT    (64L<<0)
5051 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_CSCH_SLOT_CNT   (65L<<0)
5052 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_RLUPQ_VALID_CNT     (66L<<0)
5053 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_RXPQ_VALID_CNT  (67L<<0)
5054 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_RXPCQ_VALID_CNT     (68L<<0)
5055 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_RV2PPQ_VALID_CNT    (69L<<0)
5056 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_RV2PMQ_VALID_CNT    (70L<<0)
5057 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_RV2PTQ_VALID_CNT    (71L<<0)
5058 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_RDMAQ_VALID_CNT     (72L<<0)
5059 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_TSCHQ_VALID_CNT     (73L<<0)
5060 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_TBDRQ_VALID_CNT     (74L<<0)
5061 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_TXPQ_VALID_CNT  (75L<<0)
5062 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_TDMAQ_VALID_CNT     (76L<<0)
5063 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_TPATQ_VALID_CNT     (77L<<0)
5064 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_TASQ_VALID_CNT  (78L<<0)
5065 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_CSQ_VALID_CNT   (79L<<0)
5066 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_CPQ_VALID_CNT   (80L<<0)
5067 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_COMXQ_VALID_CNT     (81L<<0)
5068 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_COMTQ_VALID_CNT     (82L<<0)
5069 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_COMQ_VALID_CNT  (83L<<0)
5070 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_MGMQ_VALID_CNT  (84L<<0)
5071 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_DMAE_READ_TRANSFERS_CNT     (85L<<0)
5072 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_DMAE_READ_DELAY_PCI_CLKS_CNT    (86L<<0)
5073 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_DMAE_BIG_READ_TRANSFERS_CNT     (87L<<0)
5074 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_DMAE_BIG_READ_DELAY_PCI_CLKS_CNT    (88L<<0)
5075 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_DMAE_BIG_READ_RETRY_AFTER_DATA_CNT  (89L<<0)
5076 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_DMAE_WRITE_TRANSFERS_CNT    (90L<<0)
5077 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_DMAE_WRITE_DELAY_PCI_CLKS_CNT   (91L<<0)
5078 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_DMAE_BIG_WRITE_TRANSFERS_CNT    (92L<<0)
5079 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_DMAE_BIG_WRITE_DELAY_PCI_CLKS_CNT   (93L<<0)
5080 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_DMAE_BIG_WRITE_RETRY_AFTER_DATA_CNT     (94L<<0)
5081 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_CTX_WR_CNT64    (95L<<0)
5082 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_CTX_RD_CNT64    (96L<<0)
5083 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_CTX_ACC_STALL_CLKS  (97L<<0)
5084 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_CTX_LOCK_STALL_CLKS     (98L<<0)
5085 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_MBQ_CTX_ACCESS_STAT     (99L<<0)
5086 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_MBQ_CTX_ACCESS64_STAT   (100L<<0)
5087 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_MBQ_PCI_STALL_STAT  (101L<<0)
5088 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_TBDR_FTQ_ENTRY_CNT  (102L<<0)
5089 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_TBDR_BURST_CNT  (103L<<0)
5090 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_TDMA_FTQ_ENTRY_CNT  (104L<<0)
5091 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_TDMA_BURST_CNT  (105L<<0)
5092 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_RDMA_FTQ_ENTRY_CNT  (106L<<0)
5093 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_RDMA_BURST_CNT  (107L<<0)
5094 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_RLUP_MATCH_CNT  (108L<<0)
5095 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_TMR_POLL_PASS_CNT   (109L<<0)
5096 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_TMR_TMR1_CNT    (110L<<0)
5097 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_TMR_TMR2_CNT    (111L<<0)
5098 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_TMR_TMR3_CNT    (112L<<0)
5099 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_TMR_TMR4_CNT    (113L<<0)
5100 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_TMR_TMR5_CNT    (114L<<0)
5101 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_RV2P_STAT0  (115L<<0)
5102 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_RV2P_STAT1  (116L<<0)
5103 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_RV2P_STAT2  (117L<<0)
5104 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_RV2P_STAT3  (118L<<0)
5105 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_RV2P_STAT4  (119L<<0)
5106 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_RV2P_STAT5  (120L<<0)
5107 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_RBDC_PROC1_MISS     (121L<<0)
5108 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_RBDC_PROC2_MISS     (122L<<0)
5109 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_RBDC_BURST_CNT  (127L<<0)
5110 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_1         (0x7fL<<8)
5111 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_2         (0x7fL<<16)
5112 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_3         (0x7fL<<24)
5113 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_XI      (0xffL<<0)
5114 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_UMP_RX_FRAME_DROP_XI    (52L<<0)
5115 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_UNUSED_S0_XI    (57L<<0)
5116 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_UNUSED_S1_XI    (58L<<0)
5117 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_UNUSED_S2_XI    (85L<<0)
5118 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_UNUSED_S3_XI    (86L<<0)
5119 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_UNUSED_S4_XI    (87L<<0)
5120 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_UNUSED_S5_XI    (88L<<0)
5121 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_UNUSED_S6_XI    (89L<<0)
5122 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_UNUSED_S7_XI    (90L<<0)
5123 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_UNUSED_S8_XI    (91L<<0)
5124 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_UNUSED_S9_XI    (92L<<0)
5125 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_UNUSED_S10_XI   (93L<<0)
5126 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_MQ_IDB_OFLOW_XI     (94L<<0)
5127 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_CTX_BLK_RD_CNT_XI   (123L<<0)
5128 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_CTX_BLK_WR_CNT_XI   (124L<<0)
5129 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_CTX_HITS_XI     (125L<<0)
5130 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_CTX_MISSES_XI   (126L<<0)
5131 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_NUM_STATUS_BLOCKS_VEC1_XI    (128L<<0)
5132 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_NUM_INT_GEN_VEC1_XI  (129L<<0)
5133 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_NUM_INT_MBOX_WR_VEC1_XI  (130L<<0)
5134 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_CORE_CLKS_TO_HW_INTACK_VEC1_XI   (131L<<0)
5135 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_CORE_CLKS_TO_SW_INTACK_VEC1_XI   (132L<<0)
5136 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_CORE_CLKS_DURING_SW_INTACK_VEC1_XI   (133L<<0)
5137 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_NUM_STATUS_BLOCKS_VEC2_XI    (134L<<0)
5138 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_NUM_INT_GEN_VEC2_XI  (135L<<0)
5139 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_NUM_INT_MBOX_WR_VEC2_XI  (136L<<0)
5140 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_CORE_CLKS_TO_HW_INTACK_VEC2_XI   (137L<<0)
5141 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_CORE_CLKS_TO_SW_INTACK_VEC2_XI   (138L<<0)
5142 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_CORE_CLKS_DURING_SW_INTACK_VEC2_XI   (139L<<0)
5143 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_NUM_STATUS_BLOCKS_VEC3_XI    (140L<<0)
5144 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_NUM_INT_GEN_VEC3_XI  (141L<<0)
5145 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_NUM_INT_MBOX_WR_VEC3_XI  (142L<<0)
5146 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_CORE_CLKS_TO_HW_INTACK_VEC3_XI   (143L<<0)
5147 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_CORE_CLKS_TO_SW_INTACK_VEC3_XI   (144L<<0)
5148 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_CORE_CLKS_DURING_SW_INTACK_VEC3_XI   (145L<<0)
5149 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_NUM_STATUS_BLOCKS_VEC4_XI    (146L<<0)
5150 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_NUM_INT_GEN_VEC4_XI  (147L<<0)
5151 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_NUM_INT_MBOX_WR_VEC4_XI  (148L<<0)
5152 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_CORE_CLKS_TO_HW_INTACK_VEC4_XI   (149L<<0)
5153 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_CORE_CLKS_TO_SW_INTACK_VEC4_XI   (150L<<0)
5154 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_CORE_CLKS_DURING_SW_INTACK_VEC4_XI   (151L<<0)
5155 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_NUM_STATUS_BLOCKS_VEC5_XI    (152L<<0)
5156 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_NUM_INT_GEN_VEC5_XI  (153L<<0)
5157 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_NUM_INT_MBOX_WR_VEC5_XI  (154L<<0)
5158 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_CORE_CLKS_TO_HW_INTACK_VEC5_XI   (155L<<0)
5159 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_CORE_CLKS_TO_SW_INTACK_VEC5_XI   (156L<<0)
5160 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_CORE_CLKS_DURING_SW_INTACK_VEC5_XI   (157L<<0)
5161 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_NUM_STATUS_BLOCKS_VEC6_XI    (158L<<0)
5162 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_NUM_INT_GEN_VEC6_XI  (159L<<0)
5163 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_NUM_INT_MBOX_WR_VEC6_XI  (160L<<0)
5164 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_CORE_CLKS_TO_HW_INTACK_VEC6_XI   (161L<<0)
5165 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_CORE_CLKS_TO_SW_INTACK_VEC6_XI   (162L<<0)
5166 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_CORE_CLKS_DURING_SW_INTACK_VEC6_XI   (163L<<0)
5167 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_NUM_STATUS_BLOCKS_VEC7_XI    (164L<<0)
5168 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_NUM_INT_GEN_VEC7_XI  (165L<<0)
5169 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_NUM_INT_MBOX_WR_VEC7_XI  (166L<<0)
5170 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_CORE_CLKS_TO_HW_INTACK_VEC7_XI   (167L<<0)
5171 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_CORE_CLKS_TO_SW_INTACK_VEC7_XI   (168L<<0)
5172 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_CORE_CLKS_DURING_SW_INTACK_VEC7_XI   (169L<<0)
5173 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_NUM_STATUS_BLOCKS_VEC8_XI    (170L<<0)
5174 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_NUM_INT_GEN_VEC8_XI  (171L<<0)
5175 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_NUM_INT_MBOX_WR_VEC8_XI  (172L<<0)
5176 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_CORE_CLKS_TO_HW_INTACK_VEC8_XI   (173L<<0)
5177 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_CORE_CLKS_TO_SW_INTACK_VEC8_XI   (174L<<0)
5178 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_CORE_CLKS_DURING_SW_INTACK_VEC8_XI   (175L<<0)
5179 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_RV2PCS_CMD_CNT_XI   (176L<<0)
5180 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_RV2PCS_SLOT_CNT_XI  (177L<<0)
5181 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_RV2PCSQ_VALID_CNT_XI    (178L<<0)
5182 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_1_XI      (0xffL<<8)
5183 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_2_XI      (0xffL<<16)
5184 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_3_XI      (0xffL<<24)
5185 
5186 #define BNX2_HC_STAT_GEN_SEL_1              0x00006854
5187 #define BNX2_HC_STAT_GEN_SEL_1_GEN_SEL_4         (0x7fL<<0)
5188 #define BNX2_HC_STAT_GEN_SEL_1_GEN_SEL_5         (0x7fL<<8)
5189 #define BNX2_HC_STAT_GEN_SEL_1_GEN_SEL_6         (0x7fL<<16)
5190 #define BNX2_HC_STAT_GEN_SEL_1_GEN_SEL_7         (0x7fL<<24)
5191 #define BNX2_HC_STAT_GEN_SEL_1_GEN_SEL_4_XI      (0xffL<<0)
5192 #define BNX2_HC_STAT_GEN_SEL_1_GEN_SEL_5_XI      (0xffL<<8)
5193 #define BNX2_HC_STAT_GEN_SEL_1_GEN_SEL_6_XI      (0xffL<<16)
5194 #define BNX2_HC_STAT_GEN_SEL_1_GEN_SEL_7_XI      (0xffL<<24)
5195 
5196 #define BNX2_HC_STAT_GEN_SEL_2              0x00006858
5197 #define BNX2_HC_STAT_GEN_SEL_2_GEN_SEL_8         (0x7fL<<0)
5198 #define BNX2_HC_STAT_GEN_SEL_2_GEN_SEL_9         (0x7fL<<8)
5199 #define BNX2_HC_STAT_GEN_SEL_2_GEN_SEL_10        (0x7fL<<16)
5200 #define BNX2_HC_STAT_GEN_SEL_2_GEN_SEL_11        (0x7fL<<24)
5201 #define BNX2_HC_STAT_GEN_SEL_2_GEN_SEL_8_XI      (0xffL<<0)
5202 #define BNX2_HC_STAT_GEN_SEL_2_GEN_SEL_9_XI      (0xffL<<8)
5203 #define BNX2_HC_STAT_GEN_SEL_2_GEN_SEL_10_XI         (0xffL<<16)
5204 #define BNX2_HC_STAT_GEN_SEL_2_GEN_SEL_11_XI         (0xffL<<24)
5205 
5206 #define BNX2_HC_STAT_GEN_SEL_3              0x0000685c
5207 #define BNX2_HC_STAT_GEN_SEL_3_GEN_SEL_12        (0x7fL<<0)
5208 #define BNX2_HC_STAT_GEN_SEL_3_GEN_SEL_13        (0x7fL<<8)
5209 #define BNX2_HC_STAT_GEN_SEL_3_GEN_SEL_14        (0x7fL<<16)
5210 #define BNX2_HC_STAT_GEN_SEL_3_GEN_SEL_15        (0x7fL<<24)
5211 #define BNX2_HC_STAT_GEN_SEL_3_GEN_SEL_12_XI         (0xffL<<0)
5212 #define BNX2_HC_STAT_GEN_SEL_3_GEN_SEL_13_XI         (0xffL<<8)
5213 #define BNX2_HC_STAT_GEN_SEL_3_GEN_SEL_14_XI         (0xffL<<16)
5214 #define BNX2_HC_STAT_GEN_SEL_3_GEN_SEL_15_XI         (0xffL<<24)
5215 
5216 #define BNX2_HC_STAT_GEN_STAT0              0x00006888
5217 #define BNX2_HC_STAT_GEN_STAT1              0x0000688c
5218 #define BNX2_HC_STAT_GEN_STAT2              0x00006890
5219 #define BNX2_HC_STAT_GEN_STAT3              0x00006894
5220 #define BNX2_HC_STAT_GEN_STAT4              0x00006898
5221 #define BNX2_HC_STAT_GEN_STAT5              0x0000689c
5222 #define BNX2_HC_STAT_GEN_STAT6              0x000068a0
5223 #define BNX2_HC_STAT_GEN_STAT7              0x000068a4
5224 #define BNX2_HC_STAT_GEN_STAT8              0x000068a8
5225 #define BNX2_HC_STAT_GEN_STAT9              0x000068ac
5226 #define BNX2_HC_STAT_GEN_STAT10             0x000068b0
5227 #define BNX2_HC_STAT_GEN_STAT11             0x000068b4
5228 #define BNX2_HC_STAT_GEN_STAT12             0x000068b8
5229 #define BNX2_HC_STAT_GEN_STAT13             0x000068bc
5230 #define BNX2_HC_STAT_GEN_STAT14             0x000068c0
5231 #define BNX2_HC_STAT_GEN_STAT15             0x000068c4
5232 #define BNX2_HC_STAT_GEN_STAT_AC0           0x000068c8
5233 #define BNX2_HC_STAT_GEN_STAT_AC1           0x000068cc
5234 #define BNX2_HC_STAT_GEN_STAT_AC2           0x000068d0
5235 #define BNX2_HC_STAT_GEN_STAT_AC3           0x000068d4
5236 #define BNX2_HC_STAT_GEN_STAT_AC4           0x000068d8
5237 #define BNX2_HC_STAT_GEN_STAT_AC5           0x000068dc
5238 #define BNX2_HC_STAT_GEN_STAT_AC6           0x000068e0
5239 #define BNX2_HC_STAT_GEN_STAT_AC7           0x000068e4
5240 #define BNX2_HC_STAT_GEN_STAT_AC8           0x000068e8
5241 #define BNX2_HC_STAT_GEN_STAT_AC9           0x000068ec
5242 #define BNX2_HC_STAT_GEN_STAT_AC10          0x000068f0
5243 #define BNX2_HC_STAT_GEN_STAT_AC11          0x000068f4
5244 #define BNX2_HC_STAT_GEN_STAT_AC12          0x000068f8
5245 #define BNX2_HC_STAT_GEN_STAT_AC13          0x000068fc
5246 #define BNX2_HC_STAT_GEN_STAT_AC14          0x00006900
5247 #define BNX2_HC_STAT_GEN_STAT_AC15          0x00006904
5248 #define BNX2_HC_STAT_GEN_STAT_AC            0x000068c8
5249 #define BNX2_HC_VIS                 0x00006908
5250 #define BNX2_HC_VIS_STAT_BUILD_STATE             (0xfL<<0)
5251 #define BNX2_HC_VIS_STAT_BUILD_STATE_IDLE        (0L<<0)
5252 #define BNX2_HC_VIS_STAT_BUILD_STATE_START       (1L<<0)
5253 #define BNX2_HC_VIS_STAT_BUILD_STATE_REQUEST         (2L<<0)
5254 #define BNX2_HC_VIS_STAT_BUILD_STATE_UPDATE64        (3L<<0)
5255 #define BNX2_HC_VIS_STAT_BUILD_STATE_UPDATE32        (4L<<0)
5256 #define BNX2_HC_VIS_STAT_BUILD_STATE_UPDATE_DONE     (5L<<0)
5257 #define BNX2_HC_VIS_STAT_BUILD_STATE_DMA         (6L<<0)
5258 #define BNX2_HC_VIS_STAT_BUILD_STATE_MSI_CONTROL     (7L<<0)
5259 #define BNX2_HC_VIS_STAT_BUILD_STATE_MSI_LOW         (8L<<0)
5260 #define BNX2_HC_VIS_STAT_BUILD_STATE_MSI_HIGH        (9L<<0)
5261 #define BNX2_HC_VIS_STAT_BUILD_STATE_MSI_DATA        (10L<<0)
5262 #define BNX2_HC_VIS_DMA_STAT_STATE           (0xfL<<8)
5263 #define BNX2_HC_VIS_DMA_STAT_STATE_IDLE          (0L<<8)
5264 #define BNX2_HC_VIS_DMA_STAT_STATE_STATUS_PARAM      (1L<<8)
5265 #define BNX2_HC_VIS_DMA_STAT_STATE_STATUS_DMA        (2L<<8)
5266 #define BNX2_HC_VIS_DMA_STAT_STATE_WRITE_COMP        (3L<<8)
5267 #define BNX2_HC_VIS_DMA_STAT_STATE_COMP          (4L<<8)
5268 #define BNX2_HC_VIS_DMA_STAT_STATE_STATISTIC_PARAM   (5L<<8)
5269 #define BNX2_HC_VIS_DMA_STAT_STATE_STATISTIC_DMA     (6L<<8)
5270 #define BNX2_HC_VIS_DMA_STAT_STATE_WRITE_COMP_1      (7L<<8)
5271 #define BNX2_HC_VIS_DMA_STAT_STATE_WRITE_COMP_2      (8L<<8)
5272 #define BNX2_HC_VIS_DMA_STAT_STATE_WAIT          (9L<<8)
5273 #define BNX2_HC_VIS_DMA_STAT_STATE_ABORT         (15L<<8)
5274 #define BNX2_HC_VIS_DMA_MSI_STATE            (0x7L<<12)
5275 #define BNX2_HC_VIS_STATISTIC_DMA_EN_STATE       (0x3L<<15)
5276 #define BNX2_HC_VIS_STATISTIC_DMA_EN_STATE_IDLE      (0L<<15)
5277 #define BNX2_HC_VIS_STATISTIC_DMA_EN_STATE_COUNT     (1L<<15)
5278 #define BNX2_HC_VIS_STATISTIC_DMA_EN_STATE_START     (2L<<15)
5279 
5280 #define BNX2_HC_VIS_1                   0x0000690c
5281 #define BNX2_HC_VIS_1_HW_INTACK_STATE            (1L<<4)
5282 #define BNX2_HC_VIS_1_HW_INTACK_STATE_IDLE       (0L<<4)
5283 #define BNX2_HC_VIS_1_HW_INTACK_STATE_COUNT      (1L<<4)
5284 #define BNX2_HC_VIS_1_SW_INTACK_STATE            (1L<<5)
5285 #define BNX2_HC_VIS_1_SW_INTACK_STATE_IDLE       (0L<<5)
5286 #define BNX2_HC_VIS_1_SW_INTACK_STATE_COUNT      (1L<<5)
5287 #define BNX2_HC_VIS_1_DURING_SW_INTACK_STATE         (1L<<6)
5288 #define BNX2_HC_VIS_1_DURING_SW_INTACK_STATE_IDLE    (0L<<6)
5289 #define BNX2_HC_VIS_1_DURING_SW_INTACK_STATE_COUNT   (1L<<6)
5290 #define BNX2_HC_VIS_1_MAILBOX_COUNT_STATE        (1L<<7)
5291 #define BNX2_HC_VIS_1_MAILBOX_COUNT_STATE_IDLE       (0L<<7)
5292 #define BNX2_HC_VIS_1_MAILBOX_COUNT_STATE_COUNT      (1L<<7)
5293 #define BNX2_HC_VIS_1_RAM_RD_ARB_STATE           (0xfL<<17)
5294 #define BNX2_HC_VIS_1_RAM_RD_ARB_STATE_IDLE      (0L<<17)
5295 #define BNX2_HC_VIS_1_RAM_RD_ARB_STATE_DMA       (1L<<17)
5296 #define BNX2_HC_VIS_1_RAM_RD_ARB_STATE_UPDATE        (2L<<17)
5297 #define BNX2_HC_VIS_1_RAM_RD_ARB_STATE_ASSIGN        (3L<<17)
5298 #define BNX2_HC_VIS_1_RAM_RD_ARB_STATE_WAIT      (4L<<17)
5299 #define BNX2_HC_VIS_1_RAM_RD_ARB_STATE_REG_UPDATE    (5L<<17)
5300 #define BNX2_HC_VIS_1_RAM_RD_ARB_STATE_REG_ASSIGN    (6L<<17)
5301 #define BNX2_HC_VIS_1_RAM_RD_ARB_STATE_REG_WAIT      (7L<<17)
5302 #define BNX2_HC_VIS_1_RAM_WR_ARB_STATE           (0x3L<<21)
5303 #define BNX2_HC_VIS_1_RAM_WR_ARB_STATE_NORMAL        (0L<<21)
5304 #define BNX2_HC_VIS_1_RAM_WR_ARB_STATE_CLEAR         (1L<<21)
5305 #define BNX2_HC_VIS_1_INT_GEN_STATE          (1L<<23)
5306 #define BNX2_HC_VIS_1_INT_GEN_STATE_DLE          (0L<<23)
5307 #define BNX2_HC_VIS_1_INT_GEN_STATE_NTERRUPT         (1L<<23)
5308 #define BNX2_HC_VIS_1_STAT_CHAN_ID           (0x7L<<24)
5309 #define BNX2_HC_VIS_1_INT_B              (1L<<27)
5310 
5311 #define BNX2_HC_DEBUG_VECT_PEEK             0x00006910
5312 #define BNX2_HC_DEBUG_VECT_PEEK_1_VALUE          (0x7ffL<<0)
5313 #define BNX2_HC_DEBUG_VECT_PEEK_1_PEEK_EN        (1L<<11)
5314 #define BNX2_HC_DEBUG_VECT_PEEK_1_SEL            (0xfL<<12)
5315 #define BNX2_HC_DEBUG_VECT_PEEK_2_VALUE          (0x7ffL<<16)
5316 #define BNX2_HC_DEBUG_VECT_PEEK_2_PEEK_EN        (1L<<27)
5317 #define BNX2_HC_DEBUG_VECT_PEEK_2_SEL            (0xfL<<28)
5318 
5319 #define BNX2_HC_COALESCE_NOW                0x00006914
5320 #define BNX2_HC_COALESCE_NOW_COAL_NOW            (0x1ffL<<1)
5321 #define BNX2_HC_COALESCE_NOW_COAL_NOW_WO_INT         (0x1ffL<<11)
5322 #define BNX2_HC_COALESCE_NOW_COAL_ON_NXT_EVENT       (0x1ffL<<21)
5323 
5324 #define BNX2_HC_MSIX_BIT_VECTOR             0x00006918
5325 #define BNX2_HC_MSIX_BIT_VECTOR_VAL          (0x1ffL<<0)
5326 
5327 #define BNX2_HC_SB_CONFIG_1             0x00006a00
5328 #define BNX2_HC_SB_CONFIG_1_RX_TMR_MODE          (1L<<1)
5329 #define BNX2_HC_SB_CONFIG_1_TX_TMR_MODE          (1L<<2)
5330 #define BNX2_HC_SB_CONFIG_1_COM_TMR_MODE         (1L<<3)
5331 #define BNX2_HC_SB_CONFIG_1_CMD_TMR_MODE         (1L<<4)
5332 #define BNX2_HC_SB_CONFIG_1_PER_MODE             (1L<<16)
5333 #define BNX2_HC_SB_CONFIG_1_ONE_SHOT             (1L<<17)
5334 #define BNX2_HC_SB_CONFIG_1_USE_INT_PARAM        (1L<<18)
5335 #define BNX2_HC_SB_CONFIG_1_PER_COLLECT_LIMIT        (0xfL<<20)
5336 
5337 #define BNX2_HC_TX_QUICK_CONS_TRIP_1            0x00006a04
5338 #define BNX2_HC_TX_QUICK_CONS_TRIP_1_VALUE       (0xffL<<0)
5339 #define BNX2_HC_TX_QUICK_CONS_TRIP_1_INT         (0xffL<<16)
5340 
5341 #define BNX2_HC_COMP_PROD_TRIP_1            0x00006a08
5342 #define BNX2_HC_COMP_PROD_TRIP_1_VALUE           (0xffL<<0)
5343 #define BNX2_HC_COMP_PROD_TRIP_1_INT             (0xffL<<16)
5344 
5345 #define BNX2_HC_RX_QUICK_CONS_TRIP_1            0x00006a0c
5346 #define BNX2_HC_RX_QUICK_CONS_TRIP_1_VALUE       (0xffL<<0)
5347 #define BNX2_HC_RX_QUICK_CONS_TRIP_1_INT         (0xffL<<16)
5348 
5349 #define BNX2_HC_RX_TICKS_1              0x00006a10
5350 #define BNX2_HC_RX_TICKS_1_VALUE             (0x3ffL<<0)
5351 #define BNX2_HC_RX_TICKS_1_INT               (0x3ffL<<16)
5352 
5353 #define BNX2_HC_TX_TICKS_1              0x00006a14
5354 #define BNX2_HC_TX_TICKS_1_VALUE             (0x3ffL<<0)
5355 #define BNX2_HC_TX_TICKS_1_INT               (0x3ffL<<16)
5356 
5357 #define BNX2_HC_COM_TICKS_1             0x00006a18
5358 #define BNX2_HC_COM_TICKS_1_VALUE            (0x3ffL<<0)
5359 #define BNX2_HC_COM_TICKS_1_INT              (0x3ffL<<16)
5360 
5361 #define BNX2_HC_CMD_TICKS_1             0x00006a1c
5362 #define BNX2_HC_CMD_TICKS_1_VALUE            (0x3ffL<<0)
5363 #define BNX2_HC_CMD_TICKS_1_INT              (0x3ffL<<16)
5364 
5365 #define BNX2_HC_PERIODIC_TICKS_1            0x00006a20
5366 #define BNX2_HC_PERIODIC_TICKS_1_HC_PERIODIC_TICKS   (0xffffL<<0)
5367 #define BNX2_HC_PERIODIC_TICKS_1_HC_INT_PERIODIC_TICKS   (0xffffL<<16)
5368 
5369 #define BNX2_HC_SB_CONFIG_2             0x00006a24
5370 #define BNX2_HC_SB_CONFIG_2_RX_TMR_MODE          (1L<<1)
5371 #define BNX2_HC_SB_CONFIG_2_TX_TMR_MODE          (1L<<2)
5372 #define BNX2_HC_SB_CONFIG_2_COM_TMR_MODE         (1L<<3)
5373 #define BNX2_HC_SB_CONFIG_2_CMD_TMR_MODE         (1L<<4)
5374 #define BNX2_HC_SB_CONFIG_2_PER_MODE             (1L<<16)
5375 #define BNX2_HC_SB_CONFIG_2_ONE_SHOT             (1L<<17)
5376 #define BNX2_HC_SB_CONFIG_2_USE_INT_PARAM        (1L<<18)
5377 #define BNX2_HC_SB_CONFIG_2_PER_COLLECT_LIMIT        (0xfL<<20)
5378 
5379 #define BNX2_HC_TX_QUICK_CONS_TRIP_2            0x00006a28
5380 #define BNX2_HC_TX_QUICK_CONS_TRIP_2_VALUE       (0xffL<<0)
5381 #define BNX2_HC_TX_QUICK_CONS_TRIP_2_INT         (0xffL<<16)
5382 
5383 #define BNX2_HC_COMP_PROD_TRIP_2            0x00006a2c
5384 #define BNX2_HC_COMP_PROD_TRIP_2_VALUE           (0xffL<<0)
5385 #define BNX2_HC_COMP_PROD_TRIP_2_INT             (0xffL<<16)
5386 
5387 #define BNX2_HC_RX_QUICK_CONS_TRIP_2            0x00006a30
5388 #define BNX2_HC_RX_QUICK_CONS_TRIP_2_VALUE       (0xffL<<0)
5389 #define BNX2_HC_RX_QUICK_CONS_TRIP_2_INT         (0xffL<<16)
5390 
5391 #define BNX2_HC_RX_TICKS_2              0x00006a34
5392 #define BNX2_HC_RX_TICKS_2_VALUE             (0x3ffL<<0)
5393 #define BNX2_HC_RX_TICKS_2_INT               (0x3ffL<<16)
5394 
5395 #define BNX2_HC_TX_TICKS_2              0x00006a38
5396 #define BNX2_HC_TX_TICKS_2_VALUE             (0x3ffL<<0)
5397 #define BNX2_HC_TX_TICKS_2_INT               (0x3ffL<<16)
5398 
5399 #define BNX2_HC_COM_TICKS_2             0x00006a3c
5400 #define BNX2_HC_COM_TICKS_2_VALUE            (0x3ffL<<0)
5401 #define BNX2_HC_COM_TICKS_2_INT              (0x3ffL<<16)
5402 
5403 #define BNX2_HC_CMD_TICKS_2             0x00006a40
5404 #define BNX2_HC_CMD_TICKS_2_VALUE            (0x3ffL<<0)
5405 #define BNX2_HC_CMD_TICKS_2_INT              (0x3ffL<<16)
5406 
5407 #define BNX2_HC_PERIODIC_TICKS_2            0x00006a44
5408 #define BNX2_HC_PERIODIC_TICKS_2_HC_PERIODIC_TICKS   (0xffffL<<0)
5409 #define BNX2_HC_PERIODIC_TICKS_2_HC_INT_PERIODIC_TICKS   (0xffffL<<16)
5410 
5411 #define BNX2_HC_SB_CONFIG_3             0x00006a48
5412 #define BNX2_HC_SB_CONFIG_3_RX_TMR_MODE          (1L<<1)
5413 #define BNX2_HC_SB_CONFIG_3_TX_TMR_MODE          (1L<<2)
5414 #define BNX2_HC_SB_CONFIG_3_COM_TMR_MODE         (1L<<3)
5415 #define BNX2_HC_SB_CONFIG_3_CMD_TMR_MODE         (1L<<4)
5416 #define BNX2_HC_SB_CONFIG_3_PER_MODE             (1L<<16)
5417 #define BNX2_HC_SB_CONFIG_3_ONE_SHOT             (1L<<17)
5418 #define BNX2_HC_SB_CONFIG_3_USE_INT_PARAM        (1L<<18)
5419 #define BNX2_HC_SB_CONFIG_3_PER_COLLECT_LIMIT        (0xfL<<20)
5420 
5421 #define BNX2_HC_TX_QUICK_CONS_TRIP_3            0x00006a4c
5422 #define BNX2_HC_TX_QUICK_CONS_TRIP_3_VALUE       (0xffL<<0)
5423 #define BNX2_HC_TX_QUICK_CONS_TRIP_3_INT         (0xffL<<16)
5424 
5425 #define BNX2_HC_COMP_PROD_TRIP_3            0x00006a50
5426 #define BNX2_HC_COMP_PROD_TRIP_3_VALUE           (0xffL<<0)
5427 #define BNX2_HC_COMP_PROD_TRIP_3_INT             (0xffL<<16)
5428 
5429 #define BNX2_HC_RX_QUICK_CONS_TRIP_3            0x00006a54
5430 #define BNX2_HC_RX_QUICK_CONS_TRIP_3_VALUE       (0xffL<<0)
5431 #define BNX2_HC_RX_QUICK_CONS_TRIP_3_INT         (0xffL<<16)
5432 
5433 #define BNX2_HC_RX_TICKS_3              0x00006a58
5434 #define BNX2_HC_RX_TICKS_3_VALUE             (0x3ffL<<0)
5435 #define BNX2_HC_RX_TICKS_3_INT               (0x3ffL<<16)
5436 
5437 #define BNX2_HC_TX_TICKS_3              0x00006a5c
5438 #define BNX2_HC_TX_TICKS_3_VALUE             (0x3ffL<<0)
5439 #define BNX2_HC_TX_TICKS_3_INT               (0x3ffL<<16)
5440 
5441 #define BNX2_HC_COM_TICKS_3             0x00006a60
5442 #define BNX2_HC_COM_TICKS_3_VALUE            (0x3ffL<<0)
5443 #define BNX2_HC_COM_TICKS_3_INT              (0x3ffL<<16)
5444 
5445 #define BNX2_HC_CMD_TICKS_3             0x00006a64
5446 #define BNX2_HC_CMD_TICKS_3_VALUE            (0x3ffL<<0)
5447 #define BNX2_HC_CMD_TICKS_3_INT              (0x3ffL<<16)
5448 
5449 #define BNX2_HC_PERIODIC_TICKS_3            0x00006a68
5450 #define BNX2_HC_PERIODIC_TICKS_3_HC_PERIODIC_TICKS   (0xffffL<<0)
5451 #define BNX2_HC_PERIODIC_TICKS_3_HC_INT_PERIODIC_TICKS   (0xffffL<<16)
5452 
5453 #define BNX2_HC_SB_CONFIG_4             0x00006a6c
5454 #define BNX2_HC_SB_CONFIG_4_RX_TMR_MODE          (1L<<1)
5455 #define BNX2_HC_SB_CONFIG_4_TX_TMR_MODE          (1L<<2)
5456 #define BNX2_HC_SB_CONFIG_4_COM_TMR_MODE         (1L<<3)
5457 #define BNX2_HC_SB_CONFIG_4_CMD_TMR_MODE         (1L<<4)
5458 #define BNX2_HC_SB_CONFIG_4_PER_MODE             (1L<<16)
5459 #define BNX2_HC_SB_CONFIG_4_ONE_SHOT             (1L<<17)
5460 #define BNX2_HC_SB_CONFIG_4_USE_INT_PARAM        (1L<<18)
5461 #define BNX2_HC_SB_CONFIG_4_PER_COLLECT_LIMIT        (0xfL<<20)
5462 
5463 #define BNX2_HC_TX_QUICK_CONS_TRIP_4            0x00006a70
5464 #define BNX2_HC_TX_QUICK_CONS_TRIP_4_VALUE       (0xffL<<0)
5465 #define BNX2_HC_TX_QUICK_CONS_TRIP_4_INT         (0xffL<<16)
5466 
5467 #define BNX2_HC_COMP_PROD_TRIP_4            0x00006a74
5468 #define BNX2_HC_COMP_PROD_TRIP_4_VALUE           (0xffL<<0)
5469 #define BNX2_HC_COMP_PROD_TRIP_4_INT             (0xffL<<16)
5470 
5471 #define BNX2_HC_RX_QUICK_CONS_TRIP_4            0x00006a78
5472 #define BNX2_HC_RX_QUICK_CONS_TRIP_4_VALUE       (0xffL<<0)
5473 #define BNX2_HC_RX_QUICK_CONS_TRIP_4_INT         (0xffL<<16)
5474 
5475 #define BNX2_HC_RX_TICKS_4              0x00006a7c
5476 #define BNX2_HC_RX_TICKS_4_VALUE             (0x3ffL<<0)
5477 #define BNX2_HC_RX_TICKS_4_INT               (0x3ffL<<16)
5478 
5479 #define BNX2_HC_TX_TICKS_4              0x00006a80
5480 #define BNX2_HC_TX_TICKS_4_VALUE             (0x3ffL<<0)
5481 #define BNX2_HC_TX_TICKS_4_INT               (0x3ffL<<16)
5482 
5483 #define BNX2_HC_COM_TICKS_4             0x00006a84
5484 #define BNX2_HC_COM_TICKS_4_VALUE            (0x3ffL<<0)
5485 #define BNX2_HC_COM_TICKS_4_INT              (0x3ffL<<16)
5486 
5487 #define BNX2_HC_CMD_TICKS_4             0x00006a88
5488 #define BNX2_HC_CMD_TICKS_4_VALUE            (0x3ffL<<0)
5489 #define BNX2_HC_CMD_TICKS_4_INT              (0x3ffL<<16)
5490 
5491 #define BNX2_HC_PERIODIC_TICKS_4            0x00006a8c
5492 #define BNX2_HC_PERIODIC_TICKS_4_HC_PERIODIC_TICKS   (0xffffL<<0)
5493 #define BNX2_HC_PERIODIC_TICKS_4_HC_INT_PERIODIC_TICKS   (0xffffL<<16)
5494 
5495 #define BNX2_HC_SB_CONFIG_5             0x00006a90
5496 #define BNX2_HC_SB_CONFIG_5_RX_TMR_MODE          (1L<<1)
5497 #define BNX2_HC_SB_CONFIG_5_TX_TMR_MODE          (1L<<2)
5498 #define BNX2_HC_SB_CONFIG_5_COM_TMR_MODE         (1L<<3)
5499 #define BNX2_HC_SB_CONFIG_5_CMD_TMR_MODE         (1L<<4)
5500 #define BNX2_HC_SB_CONFIG_5_PER_MODE             (1L<<16)
5501 #define BNX2_HC_SB_CONFIG_5_ONE_SHOT             (1L<<17)
5502 #define BNX2_HC_SB_CONFIG_5_USE_INT_PARAM        (1L<<18)
5503 #define BNX2_HC_SB_CONFIG_5_PER_COLLECT_LIMIT        (0xfL<<20)
5504 
5505 #define BNX2_HC_TX_QUICK_CONS_TRIP_5            0x00006a94
5506 #define BNX2_HC_TX_QUICK_CONS_TRIP_5_VALUE       (0xffL<<0)
5507 #define BNX2_HC_TX_QUICK_CONS_TRIP_5_INT         (0xffL<<16)
5508 
5509 #define BNX2_HC_COMP_PROD_TRIP_5            0x00006a98
5510 #define BNX2_HC_COMP_PROD_TRIP_5_VALUE           (0xffL<<0)
5511 #define BNX2_HC_COMP_PROD_TRIP_5_INT             (0xffL<<16)
5512 
5513 #define BNX2_HC_RX_QUICK_CONS_TRIP_5            0x00006a9c
5514 #define BNX2_HC_RX_QUICK_CONS_TRIP_5_VALUE       (0xffL<<0)
5515 #define BNX2_HC_RX_QUICK_CONS_TRIP_5_INT         (0xffL<<16)
5516 
5517 #define BNX2_HC_RX_TICKS_5              0x00006aa0
5518 #define BNX2_HC_RX_TICKS_5_VALUE             (0x3ffL<<0)
5519 #define BNX2_HC_RX_TICKS_5_INT               (0x3ffL<<16)
5520 
5521 #define BNX2_HC_TX_TICKS_5              0x00006aa4
5522 #define BNX2_HC_TX_TICKS_5_VALUE             (0x3ffL<<0)
5523 #define BNX2_HC_TX_TICKS_5_INT               (0x3ffL<<16)
5524 
5525 #define BNX2_HC_COM_TICKS_5             0x00006aa8
5526 #define BNX2_HC_COM_TICKS_5_VALUE            (0x3ffL<<0)
5527 #define BNX2_HC_COM_TICKS_5_INT              (0x3ffL<<16)
5528 
5529 #define BNX2_HC_CMD_TICKS_5             0x00006aac
5530 #define BNX2_HC_CMD_TICKS_5_VALUE            (0x3ffL<<0)
5531