include/smp/apic-defs.h

0001 /*                    The Quest Operating System
0002  *  Copyright (C) 2005-2010  Richard West, Boston University
0003  *
0004  *  This program is free software: you can redistribute it and/or modify
0005  *  it under the terms of the GNU General Public License as published by
0006  *  the Free Software Foundation, either version 3 of the License, or
0007  *  (at your option) any later version.
0008  *
0009  *  This program is distributed in the hope that it will be useful,
0010  *  but WITHOUT ANY WARRANTY; without even the implied warranty of
0011  *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
0012  *  GNU General Public License for more details.
0013  *
0014  *  You should have received a copy of the GNU General Public License
0015  *  along with this program.  If not, see <http://www.gnu.org/licenses/>.
0016  */
0017
0018 /*
0019  *  <Insert copyright here : it must be BSD-like so everyone can use it>
0020  *
0021  *  Author:  Erich Boleyn  <erich@uruk.org>   http://www.uruk.org/~erich/
0022  *
0023  *  Header file for Intel Architecture local and I/O APIC definitions.
0024  *
0025  *  This file was created from information in the Intel Pentium Pro
0026  *  Family Developer's Manual, Volume 3: Operating System Writer's
0027  *  Manual, order number 242692-001, which can be ordered from the
0028  *  Intel literature center.
0029  */
0030
0031 #ifndef _APIC_DEFS_H_
0032 #define _APIC_DEFS_H_
0033
0034 /*
0035  *  APIC Defines.
0036  */
0037
0038 /*
0039  * Recommendation:  Don't use this except for MSI interrupt delivery.
0040  * In general, the "Destination Mode" can be used to control this, since
0041  * it is DIFFERENT (0xF) for Pentium and P6, but not on the same APIC
0042  * version for AMD Opteron.
0043  */
0044 #define APIC_BCAST_ID                           0xFF
0045
0046 /*
0047  *  APIC register definitions
0048  */
0049
0050 /*
0051  *  Shared defines for I/O and local APIC definitions
0052  */
0053 /* APIC version register */
0054 #define APIC_VERSION(x)                         ((x) & 0xFF)
0055 #define APIC_MAXREDIR(x)                        (((x) >> 16) & 0xFF)
0056 /* APIC id register */
0057 #define APIC_ID(x)                              ((x) >> 24)
0058 #define APIC_VER_NEW                            0x10
0059
0060 #define IOAPIC_REGSEL                           0
0061 #define IOAPIC_RW                               0x10
0062 #define         IOAPIC_ID                       0
0063 #define         IOAPIC_VER                      1
0064 #define         IOAPIC_REDIR                    0x10
0065
0066 /* Delivery Mode Masks */
0067 typedef enum {
0068   IOAPIC_DELIVERY_FIXED=                   0x000,
0069   IOAPIC_DELIVERY_LOWEST_PRIORITY=         0x100,
0070   /* the next 4 are likely unsupported: */
0071   IOAPIC_DELIVERY_SMI=                     0x200,
0072   IOAPIC_DELIVERY_NMI=                     0x400,
0073   IOAPIC_DELIVERY_INIT=                    0x500,
0074   IOAPIC_DELIVERY_EXTINT=                  0x700
0075 } IOAPIC_delivery_mode_t;
0076
0077 /* Destination Mode Masks */
0078 typedef enum {
0079   IOAPIC_DESTINATION_PHYSICAL=             0x000,
0080   IOAPIC_DESTINATION_LOGICAL=              0x800
0081 } IOAPIC_destination_mode_t;
0082
0083 /* Trigger Mode Masks */
0084 typedef enum {
0085   IOAPIC_TRIGGER_EDGE=                     0x0000,
0086   IOAPIC_TRIGGER_LEVEL=                    0x8000
0087 } IOAPIC_trigger_mode_t;
0088
0089 /* Polarity Mode Masks */
0090 typedef enum {
0091   IOAPIC_POLARITY_HIGH=                    0x0000,
0092   IOAPIC_POLARITY_LOW=                     0x2000
0093 } IOAPIC_polarity_mode_t;
0094
0095 /* Local APIC */
0096
0097 #define LAPIC_ID                                0x20
0098 #define LAPIC_VER                               0x30
0099 #define LAPIC_TPR                               0x80
0100 #define LAPIC_APR                               0x90
0101 #define LAPIC_PPR                               0xA0
0102 #define LAPIC_EOI                               0xB0
0103 #define LAPIC_LDR                               0xD0
0104 #define LAPIC_DFR                               0xE0
0105 #define LAPIC_SPIV                              0xF0
0106 #define         LAPIC_SPIV_ENABLE_APIC          0x100
0107 #define LAPIC_ISR                               0x100
0108 #define LAPIC_TMR                               0x180
0109 #define LAPIC_IRR                               0x200
0110 #define LAPIC_ESR                               0x280
0111 #define LAPIC_ICR                               0x300
0112
0113 /* The ICR consists of an int-vector ORed with the following flags: */
0114
0115 /* Destination modes: */
0116 #define         LAPIC_ICR_DS_SELF               0x40000 /* self */
0117 #define         LAPIC_ICR_DS_ALLINC             0x80000 /* all including self */
0118 #define         LAPIC_ICR_DS_ALLEX              0xC0000 /* all excluding self */
0119
0120 /* Only INIT IPI uses this: */
0121 #define         LAPIC_ICR_TM_LEVEL              0x8000  /* level vs edge mode */
0122 /* Only INIT de-assert would NOT use this: */
0123 #define         LAPIC_ICR_LEVELASSERT           0x4000  /* level assert */
0124 /* But, Pentium4 assumes other IPIs have it set, according to Intel specs */
0125 /* So... just always use it. */
0126
0127 #define         LAPIC_ICR_STATUS_PEND           0x1000  /* status check, readonly */
0128 #define         LAPIC_ICR_DM_LOGICAL            0x800   /* logical destination mode */
0129
0130 /* Delivery mode: */
0131 /* FIXED delivery is 0x0 */
0132 #define         LAPIC_ICR_DM_LOWPRI             0x100   /* send to lowest-priority CPU */
0133 #define         LAPIC_ICR_DM_SMI                0x200   /* send SMI */
0134 #define         LAPIC_ICR_DM_NMI                0x400   /* send NMI */
0135 #define         LAPIC_ICR_DM_INIT               0x500   /* send INIT */
0136 #define         LAPIC_ICR_DM_SIPI               0x600   /* send Startup IPI */
0137
0138
0139 #define LAPIC_LVTT                              0x320
0140 #define LAPIC_LVTPC                             0x340
0141 #define LAPIC_LVT0                              0x350
0142 #define LAPIC_LVT1                              0x360
0143 #define LAPIC_LVTE                              0x370
0144 #define LAPIC_TICR                              0x380
0145 #define LAPIC_TCCR                              0x390
0146 #define LAPIC_TDCR                              0x3E0
0147
0148
0149 #endif
0150
0151 /*
0152  * Local Variables:
0153  * indent-tabs-mode: nil
0154  * mode: C
0155  * c-file-style: "gnu"
0156  * c-basic-offset: 2
0157  * End:
0158  */
0159
0160 /* vi: set et sw=2 sts=2: */